We have a design using the SPI master (2.5v) and other IPs (ADC, LCD, shift regs...). When the whole design is put in hibernate the power consumption stays too high (16mA) even if peripheral sleep functions are called.
When the SPI master IP is removed, the power consumption in hibernate mode is ok (~50uA).
Is there any issues regarding the SPI IP in hibernate mode ?
Thanks in advance
Solved! Go to Solution.
yes we did it. We have no problems with the other peripherals (uart, shift reg, counter...). The SPI prevents the core to enter in hibernate. Power consumption stays around 15mA @3.3V. We check the generated code of the SPI module and we saw nothing strange.
Thanks for the answer !
Nicolas, I would suggest you to create a support case (top of this page->Design support) and get in contact to cypress directly.
How are you confirming that PSoC 3 is going into sleep mode ? Is there a functionality in main loop which stops executing ? What I mean is, only current is staying higher or CPU did not enter sleep mode itself ?
Have you called SPI component's sleep API ?
Can you check by having no wake up sources in sleep API ? This will rule out if any wake up source is misbehaving.