posedge vs negedge clocking in UDB component designs in verilog

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BuHa_1507271
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Is it safe to use negedge clocking in PSOC Verilog.  I was concerned because AN82250 PSoC® 3 PSoC 4 and PSoC 5LP Implementing Programmable Logic Designs with Verilog, on page 13...

Note To reduce the likelihood of timing and synchronization failures, it is preferable to use posedge clocking in PSoC designs.

But no further detail on why the AppNote says this.   On the other The  Warp Verilog Reference Guide doesn't seem to mention anything against negedge, and uses it in several examples.

When designing for DDR style clocking from an external source, using both posedge and negedge clocks seem needed (or to resort to a significant oversampling using an internal clock.)     Is it reasonable to ignore AN882250's advice in this case, doing something like:

always @ (posedge clock) 
begin 
. . .  something
end

always @ (negedge clock) 
begin 
. . .  something else
end

?

PSoC® 3 PSoC 4 and PSoC 5LP Implementing Programmable Logic Designs with Verilog.pdf

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Burt,

If you are worry about power consumption with I2C, you are better off using the I2C fixed function implementation. PSoC supports waking up from deep-sleep when there is activity on the I2C bus. But that only works if you use the I2C fixed function.

For the Verilog Source, you have access to the implementation of all components available in the Cypress catalog. You can either import the component, refer to PSoC Creator Tutorial - Importing and Copying Components - YouTube  , or accessing the code in the PSoC Creator installation folder at C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib

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