PSoC™ 5, 3 & 1

[gogolgoggly]

Hello, I like to control the amplitude of a clocksignal on a GPIO. I tried that with this layout:

The mux is in switch-mode.

[Len_CONSULTRON]

gogolgoggly

What are the specifications of the Output signal you are trying to achieve?

If you provide these details, we may be able to help.

[odissey1]

In your schematic, the AMux goes into Hi-Z mode on LOW, which becomes a sort of a sample-and-hold circuit. If  Pin_2 output is measured using 1MO/100pF scope probe, there likely be a steady signal. To receive modulated signal the AMux must be switched between the Pin_1 and 0V. To provide 0V to the AMux, it must be connected to external Pin,  connected to GND. 

[RodolfoGL]

If you are using PSoC 5LP, you can use the SIO pins and setup a programmable Vref with the VDAC. 

The SIO pins are only available in Port 12. You need to setup the Output drive level to Vref.

Top design screenshot:

[gogolgoggly]

Great notice, but i'm using a PSOC3.

[RodolfoGL]

This works with PSoC 3 too.

Better using one pin than 5 pins to do this...

[odissey1]

I believe the minimum output voltage that can be achieved using SIO pins with Vref is approx 0.5V, not 0V

[RodolfoGL]

Note that the Vref is only used to define the VDD for the pin. The pin will work as a digital pin, when logic is low, drives 0 V, when logic is high, drives Vref.

[gogolgoggly]

I know it's been a while. But i'm also observing this behavior. I can control the amplizude down do ~0.5V. I don't get the reason why.

[gogolgoggly · Accepted solution]

First of all thanks for your support. I've found a setup which works for me.

Iget a 2kHz signal and a 2khz signal with adjustable amplitude.

[Len_CONSULTRON]

gogolgoggly,

I'm glad you have a solution.

You might want to turn on the "Buffered output".  The VDAC8 output is normally a medium impedance. Turning on "Buffered output" will place an opamp in Follower mode (1:1 gain) and provide a much lower impedance. 

A medium impedance output can be influenced by loading.   Less so with a low impedance.

[odissey1]

hogolgoggily,

Please notice a Sync component on the schematic. It removes Setup Time Violation between the 2kHh clock and the BUS_CLOCK

[gogolgoggly]

Thanks for the tip.