PSoC™ 5, 3 & 1 Forum Discussions
I'm running into a weird intermittent problem with the UART on the PSoC 5LP(using the cy8ckit-059 eval board) where it looks like the UART component seems to miss or skip 4 bits of the serial data, and then on the next byte it gets a 'stop-bit' error if the middle bit that it thinks is the stop bit isn't a one (and otherwise it gets the wrong value).
I put in debug flags in the ISR, and I can see the interrupt gets delayed by 4 bits (there's nothing else running on the chip to cause any latency or delays, and it happens at both 57600 and 1 Mbps
This happens when it's communicating with a 'smart' servo, but if I reconfigure it to 'loopback', then it does not seem to occur.
I tried adding more decoupling capacitors to the power rails, but it didn't help.
I've attached a scope trace. The Yellow trace is the serial data, the Blue trace is the ISR flag, and the Green trace goes high once the Stop-bit error is detected.
You can see the regular spacing up until the byte just before the stop-bit flag goes high. It really looks like the UART just skips some bits.
Any thoughts or ideas?
hope you all are doing good.
I need your suggestions and help on my following tasks:
"note: a long question"
I have psoc5 lp , a mosfet (bsl802sn) and drain resistor 2.2 ohms and at source shunt resistor of 100m ohms .
My 1st-task is to maintain desired dc voltage at shunt resistor.
For this what i am doing is taking a reference volts from across shunt resistor connects it to DELSIG ADC (differential mode) in psoc 5 converts it in samples , setting a desired voltage(in between 20 to 50mv dc),implementing pid controller, calculating controlled output and send to VDAC and vdac is connected to gate of mosfet and it control the gate and maintains desired dc voltage at shunt resistor even though if I change vdd of mosfet with in a range of 2 to 4 volts , and this is working fine with some errors.
I am not sure whether this approach is good or there are some other ways for my 1st task.
my 2nd task is :
it is a continuation of 1st task in which i have to shape the output dc voltage at shunt in a rectangular wave for this i am thinking that setting two desired voltage in PID and one is zero and one is, again in between(20mv to 50mv) and oscillate between two desired voltage with frequency between 1 Hz to 2KHz hence will get rectangular wave with a high level voltage equal to our desired voltage. and here also if my vdd will change for any reason between 2 to 4 volts my desired voltage should not be change.
and for this task i am confused if this is a applicable solution to my task 2 or there are some other ways?
and 3rd task is to generate a sine wave just like a square wave. and setting a peak to peak voltage by changing desired voltage in pid in a sine wave manner.
i am not sure for all my tasks the approach i am thinking is the practical and applicable approach or there are other ways to do these tasks. let me know I will share more details if anyone does not get my point
thanks for your time to read my long query.
My links to the reference manuals are all old (Cypress) and broken.
When I search either Infineon or the community all that comes up are PSoC 4, PSoc 6, etc. , or links that don't work.
Where can I go to read/download them?
I have a question about the CY8C36 family.
1. When using ADC, internal Vref can be set to 6x, but is it structurally 6x using PGA?
2. I think it is suppressed to less than headroom (about 4.75V) at full scale, but I would like to know why Vref=1.024→6.144V can be calculated when converting ADC code to actual measured value.
3. In this case, can we consider Vref accuracy as 0.3% x 6?
Thank you in advance.Show Less
there are several differing statements about the limits of the emFile component. Does anyone have an up to date
definitive answer what the maximum card size is for the current emFile component and libraries (as downloaded from the component website) ?
And second question: has anyone lately succeeded in using a micro SD breakout SPI board with emFile or any other solution ? If yes, pls send me a link to the product that you used. I am having trouble in particular with the breakouts from China.
A recent post indicated issues with emfile.
During work with a psoc5 in 2017, I found there were some issues with Port 3 when using spi.
The post from 2017 is here:
The emFile component uses a software interrupt when there are errors, which defaults to am ARM vector table which halts the psoc. So, you can have lockup if a bad sdcard or other emFile using device is inserted.
You will have to purchase a license to get the emFile source to fix this problem, or use the open source options pointed to by others.
I don't know where to post this, so move it if necessary. I finally removed all of the proprietary part of the project, and can post it.
I have a project for a 5LP-039, a 67 mhz part, and if I use almost any clock, starting with a 66mhz clock, it gives 2 errors, that you cannot get rid of by using Sync Components (which always worked in the past) or even reducing the bus speed to 33 mhz or somewhat below. However, if you remove the DMA component, the errors go away at 66mhz! PSOC Creator 4.4
This is not posted to get I*n to work on it. They stated they will not fix any problems with PSoC creator. However, I am giving this to the wider audience of engineers so they can be aware of the issue and avoid it if possible.
The errors are (with the path name garbled on purpose) are following:
Warning: sta.M0019: PSOC_Creator_timing.html: Warning-1366: Setup time violation found in a path from clock ( CyBUS_CLK ) to clock ( CyBUS_CLK ). (File=Z:\S\_old\SurfacePanelMCU-5V0B-SPDL_OLD copy\PSOC_Creator.cydsn\PSOC_Creator_timing.html)
Warning: sta.M0019: PSOC_Creator_timing.html: Warning-1366: Setup time violation found in a path from clock ( Clock_BaudRate ) to clock ( CyBUS_CLK ). (File=Z:\S\_old\SurfacePanelMCU-5V0B-SPDL_OLD copy\PSOC_Creator.cydsn\PSOC_Creator_timing.html)
I also found that if I reduced the speed of absolutely everything to 24 mhz I could usually (not always) stamp out the CyBUS_CLK error. At that point, the sync component can fix the timing issue on the external clock.
I suspect, if I*n uses the same compiler technology for PSOC4 and PSOC6, those units may have similar issues, except for the fact that those are usually UDB crippled, with extremely few UDB's and/or extremely limited routing options, so there are fewer routing calculations that must be done. That typically means these issues won't occur.
I tried using a PSOC4 during the time I*n refused to be a manufacturer of PSOC5's, and it did not work well due to limited route-ability and limited UDB's. During that time, I*n nearly put us out of business, and I suspect that prospect makes everyone at that company very happy not to have to deal with the engineering trash we represent. I will always distrust I*n from now on. Fool me once, shame on you. Fool me twice, shame on me.
I now look for components from other manufacturers first.