PSoC™ 5, 3 & 1 Forum Discussions
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Hi, I’m the owner of the kyt cy3271 and I’m working about psoc CY8C27443-24PVXI of the RF Expansion card. I’ve the example of a filter notch made on cy8c29466-24 PXI, it has been used a LPF2 duly assessed with an excel working paper ( sent as enclosure). I would like to know what is the capacity Cpp, because in the datasheet of the LPF2 it is not present. Moreover in the file main.asm the following code is present, and I don’t know what it is for, ‘cause I don’t know the assembler very well: ; Assembly main line ;----------------------------------------------------------------------------- include "m8c.inc" ; part specific constants and macros include "memory.inc" ; Constants & macros for SMM/LMM and Compiler include "PSoCAPI.inc" ; PSoC API definitions for all User Modules export _main _main: mov A, reg[ASD11CR3] and A, ~0x04 mov reg[ASD11CR3],A mov A, 0x03 call PGA_1_Start mov A, 0x03 call LPF2_1_Start call Counter24_1_Start mov a, reg[ASD11CR1] or a, 0x1f mov reg[ASD11CR1], a ;;; .terminate: jmp .terminate |
I'm observing capsense in work.
I discovered, that baseline follows raw counts pretty well. But when raw counts are far away from baseline, the baseline
suddenly jumps up or down several hundred counts.
What is the logic behind it?
Regards
Robert
Show LessI have used sucessfully miniprog3 for I2C data exchange with PC as Master.
BUt when it came to PSOC1 The miniprog3 reads or writes wrong data!
for example :
write 04 01 (addres 4 first byte of 1) is sucessfully acknowledged up to 0B (data) (w 04+ 01+ p) and (w 04+ 0C- p)
write 04 0C up to FF doesn't get acknowledged
speed 100k on both sides, no external pullups resitors(as it was not required with psoc 3)
What is wrong?
I played with P10 and P11 pin configuration from res-pullup to open-drain-low but no success
Show LessTo get past a hurdle in a project, I've recently written a disassembler for the PSoC 1. The source is in C and compiles with GCC under Cygwin or Linux (and probably anything else, it's all pretty generic stuff).
For more details, please see the project page at code.google.com/p/m8cdis/
Suggestions, improvements, etc welcome. My email address is in the README file, or you can submit it as an issue.
--jcwren
Show LessHi,
In the Figure 24-14. Shift Operation pg 212 PSoC3, PSoC5 Architecture TRM, Document No. 001-50235 Rev *D
There is 2 (sil) instead of (sor) and (sir) (on the right side)
Jean-Louis
Show LessBecause USBFS pins is behind CY7C68013A-56LFXC CY7C68013A-56LFXC (another chip with hidden firmware)
I guess USBFS functionality cannot be tested on this kit!!!
Am I right?
robert seczkowski
Show LessThis is a chapter from latest PSOC Creator Errata:
"11. CapSense Use of a PRS with the CSD algorithm is not
supported. PRS configuration should be set to None. This will be corrected in a future release. "
What happened?
Will PRS for CapSENSE be no loner supported?
Regards
Robert Seczkowski
Show Lessled blinking , pwm 8 controled led and at the end, ezi2c in slave mode.
i have assigned pins 7 ^ 5 in the properties of the control as sda ^ scl.
The intention was to controll some variables using
the Bridge control panel.
in this last test, after program the FTMF the blue led on the FTPC stop flashing , and is
not possible to program again the FTMF. if i remove the module, the blue led blink again.. if i conect the FTMF the FTPC appears as disconected.
There is some way to recover from this point ?
thankyou Show Less