PSoC™ 5, 3 & 1 Forum Discussions

 Hi,

I am trying to design a USB to SPI converter with 24 data bits per word. How can I increase the number of data bits in the SPIM & SPIS components? 

Hello,

I use a "Up and Down" counter ( 32 bits ) configured as follows :

-period : 4294967295 (2^32  - 1)

-clock mode : count input and direction

-run mode : continuous

-reload counter on "reset" and on "tc"

Besides my input pin is configured in "resistive pull down" as drive mode, my goal is to count rising edge of a rotary encoder (in order to know the position of a robot), however my problem is when I turn my encoder the counter increment too fast whereas I turn a little bit the encoder. What's the problem ?

Thanks.

PS : I'm French what explain the quality of my English, I joined the project with the post, the name of the counter is "Counter_debug" in the PSOC Creator project!

I updated my Designer 5.1 to 5.1 SP1 with two computers. One is working and the other one doesn't work. The sypotom is that when I open a project, a fail prompt shown in screen as above. Then I uninstalled the SP1 and installed Designer 5.1. But when I open a project, the same fail message appeared. Can somebody help me out with this problem?
 

I've done it example project is USBFS Bootloader for PSoC® 3 and PSoC 5(EP64299) in PSoC5. Also I worked to size up bootloader code. However, it doesn't work after making size up source.

For example I enlarged the bootloader flash size to 74640 of 26144 bytes. In other words, flash sizes are gonna be larger than 64kb. Then I wrote bootloadable code to flash memory via USB but it doesn't work. I don't know why.

Please let me know if you know the reason.

Best regards,

Lee.

Welcome to the Cortex-M3 PSoC 5 Design Challenge, brought to you by ARM, EETimes and Cypress.  In this forum you will be able to track all of the latest announcements regarding this exciting design challenge.

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-Bobby

I have been using the 1.20 UART on an RS-485 bus configuration and the network ceases to operate when undating to 1.50 (I changed the number of bits setting after the update, but nothing else).

When I put a logic analyzer on the bus it looks like the 1.20 version introduced a slight amount of inter-byte delay, as indicated by little pulses on the Tx Enable line, but this is not so with the 1.50 version. I am only sending about 12 bytes in a typical packet, but this seems to be long enough for differences in the baud rate clocks to create a CRC error.

When I stop using buffered transmission and thus introduce a small inter-byte delay, the network operates as before.

What I would really like to be able to do (and have for the last 10 years) is set the number of stop bits for Tx to 2 and set Rx to 1. This would be a simple way to still use buffered transmission and get a little delay for re-framing each byte. There may be a way to select an inter-byte delay through the API, but I haven't found it.

I'm curious if others have faced the same situation, and what some possible solutions are. Plus if enough chime in, may Cypress will address this...

Thanks, Jim

Sir,

   We completed making our abstrat on our topic but when we put our model on the PSoc Creator we are facing a problem. we completed analog part of our model on the PSoc Creator but when we come to Digital part I have a doubt that we have to place complete REGISTER TRANSFER LEVEL Diagram in the PSOC Creator or not? OR else I roughly draw block diagrams mentioning their functionality?

   Please also mention us which family of PSoc5 we will be using in our further stages ?

    Awaiting for our reply,

Regards,

Narra.

I have 2 projects on my list, one with the block diagram and one with the creator project. Request the admin to merge them into one.

Thank You.

When can we expect ES3 samples to be available to try out?

Regards,

Dan.