PSoC™ 5, 3 & 1 Forum Discussions
I'm trying to design the drivers for a JR 8717 to make it control an arm, but it doesn't move. I used a PWM component with a clock at 1.28 khz, 8-bit resolution, UDB, one ouput, with a period of 255 and a cmp value of 22. What did I do wrong? Should the period be 20 with a cmp value of 2?
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i am using 2 UARTs, both are operating in interrupt mode 1UART is working fine. coming 2nd UART i am getting interrupt only one time after power on after that i am not getting what mght be the problem?
Thanks & Regards
V.Vishnu kumar
Show LessOn rare occasions, I get an I2C receiver hangup in a CY7C64215 when the USB I/F is active at the same time as the I2C. This appears to be corrolated with a negative over-shoot of the USB signals at the end of a frame (when both differential lines are driven low on the same clock edge).
I can detect when this happens to the I2C I/F, but have not been able to extract it from this condition via any of the API routines and can only get I2C working again via a full POR. Is there a register bit that I can toggle that does the same thing as a POR to the I2C hardware?
I've attached an oscope image of the USB frame (top trace) and the reflection of the glitch in the I2C signal (bottom trace). This was taken with the I2C signals in high-Z GPIO mode to better show how the glitch propagates between the USB and the I2C driver circuits.
Thanks Much - David G.
Show LessGood morning!
I am using Timer8 and UART modules in my design.Here is the problem:
in order to use Timer8 to generate a specific time,I have to set the global resources as follows: sysClk:6Mhz; VC1=sysClk/N:16; Vc2=Vc1/N:15; VC3 source:VC2; VC3 divider:100. the VC3 is used as Timer8's clock;
But in order to use UART modules,I have to get a baud rate of 19200,and i have to set the global resources as follows: sysClk:24Mhz;
VC3 source:SysClk/1; VC3 divider:156. the VC3 is used as Timer8's clock;
so,this is the question,i don't know how to set the global resources to satisfy the both modules,i really don't know how to solve the problem,hope you can help me ,Thank you !
Show LessMy ability to work with psoc ended up the day when I upgrader Psoc Programmer to new version 3.12.
Now CygInstaller crashes and do not allow to update anything.
Upgrading by directly downloading from the WEB does the same, installed crash more less in the middle of installation
Thanks for any hint
Regards
Robert
Show Lessam using psoc designer 5.0. i am unable debug my program.
just like in keil , is it possible to debug programs in psoc designer 5.0.
Thanking u
Show LessA new PSOC 3 development kit is available NOW: CY8CKIT-030 (www.cypress.com/go/cy8ckit-030)
This kit enables you to evaluate, develop and prototype high precision analog, low-power and low-voltage applications powered by Cypress’s CY8C38 high precision analog device family. Additionally, this kit supports the PSOC Expansion Board Kit ecosystem as a compatible host platform.
CY8CKIT-030 is equipped with our PSoC 3 production silicon.
This kit offers a lower cost option for PSoC 3 development compared to the PSoC 1/3/5 DVK (CY8CKIT-001 www.cypress.com/go/cy8ckit-001).
Also, kindly reminder that The PSoC 3 Processor Module (CY8CKIT-009), PSoC 1/3/5 DVK (CY8CKIT-001) and PSoC 3 First Touch Kit (CY8CKIT-003) are currently equipped with ES2 silicon. Our Production silicon is now available, and we would like to offer our customers the opportunity to upgrade their Kits with our production silicon. This upgrade is free of charge to our valued customers.
More details to follow of how to obtain the upgraded modules.
The upgraded module will be available starting 01-May. We will start processing orders shortly thereafter.
I am using three PGA's a project to buffer R/C filtered PWM outputs. All are configured with a gain of 1. I am using a CY8C3866PVI-021ES2 for the development. The problem PGA has input on P2_6 and the output on P2_4. If I bypass the PGA with internal routing I see the signal on P2_4 range from about 0V to about 5V as expected per the PWM output. If route through the PGA the maximum output voltage is about 2.6V. I connected a VDAC8 to the PGA input and saw about the same results. I get a slightly higher output when the PGA power is increased. Is this an ES2 problem or a Creator problem?
Placement looks like this:
@[Chip=0][FFB(SC,2)]: \PGA_0_10:SC\
SC[2]
SC[3]
@[Chip=0][FFB(SC,3)]:
\PGA_0_1:SC\
SC[0]
@[Chip=0][FFB(SC,0)] : \PGA_4_20:SC\I tried to force other usage with the directive
PGA_4_20:SC ForceComponentFixed F(SC,1) but it was ignored during synthesis. Any ideas?
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