PSoC™ 5, 3 & 1 Forum Discussions
i hope you can help me a little bit.
At the moment I am trying to program a PSoC 5 (CY8C5268LTI-LP030) with the CommandLineInterface.
Unfortunatey it isn´t working properly 😞
What have I done...
At the moment I am using this commands in a script:
OpenPort KitProg/0720063201324400 C:\Program Files (x86)\Cypress\Programmer
PSoC3_ProgramRowFromHex 0x03 0 0
Till the command "PSoC3_ProgramRowFromHex 0x03 0 0 " everything looks good. But while using this command I get following error message:
"PSoC3_ProgramRowFromHex 0x03 0 0
Timeout of SPC polling. Lost communication with chip (Status = 0x00)
PSoC3_ProgramRowFromHex 0x03 0 0 returned 80004005
And I am not sure how to fix it. I don´t know the problem... Is there anybody with an idea how to fix it?
Is there a command to program the whole hexfile without the rowId and arrayId? For example the command Program(). Unfortunately the UserGuid tells me it is only for PsoC1 😞
And is the arrayId 0x03 the correct id?
Many thanks in advance. I hope somebody can help me! 🙂
Ando some more informationen.
I am using a KitProg2 and the programming with PsocCreator oder PscoCProgrammer is working without any problems. So I guess there is no hardwareproblem.
am using psoc designer 5.0. i am unable debug my program.
just like in keil , is it possible to debug programs in psoc designer 5.0.
Thanking uShow Less
A new PSOC 3 development kit is available NOW: CY8CKIT-030 (www.cypress.com/go/cy8ckit-030)
This kit enables you to evaluate, develop and prototype high precision analog, low-power and low-voltage applications powered by Cypress’s CY8C38 high precision analog device family. Additionally, this kit supports the PSOC Expansion Board Kit ecosystem as a compatible host platform.
CY8CKIT-030 is equipped with our PSoC 3 production silicon.
This kit offers a lower cost option for PSoC 3 development compared to the PSoC 1/3/5 DVK (CY8CKIT-001 www.cypress.com/go/cy8ckit-001).
Also, kindly reminder that The PSoC 3 Processor Module (CY8CKIT-009), PSoC 1/3/5 DVK (CY8CKIT-001) and PSoC 3 First Touch Kit (CY8CKIT-003) are currently equipped with ES2 silicon. Our Production silicon is now available, and we would like to offer our customers the opportunity to upgrade their Kits with our production silicon. This upgrade is free of charge to our valued customers.
More details to follow of how to obtain the upgraded modules.
The upgraded module will be available starting 01-May. We will start processing orders shortly thereafter.
I am using three PGA's a project to buffer R/C filtered PWM outputs. All are configured with a gain of 1. I am using a CY8C3866PVI-021ES2 for the development. The problem PGA has input on P2_6 and the output on P2_4. If I bypass the PGA with internal routing I see the signal on P2_4 range from about 0V to about 5V as expected per the PWM output. If route through the PGA the maximum output voltage is about 2.6V. I connected a VDAC8 to the PGA input and saw about the same results. I get a slightly higher output when the PGA power is increased. Is this an ES2 problem or a Creator problem?
Placement looks like this:
SC@[Chip=0][FFB(SC,0)] : \PGA_4_20:SC\
I tried to force other usage with the directive
PGA_4_20:SC ForceComponentFixed F(SC,1) but it was ignored during synthesis. Any ideas?Show Less
My design uses an external power monitor/watchdog driving XRES for PUR and Watchdog functions. Unfortunately the Miniprog3 also uses XRES. Any suggestions on how to overdrive the external XRES signal (the watchdog will timeout during programming). I could use something like a resistor to isolate the external XRES, but I have no idea on the miniprog drive strength, and whether it can successfully overdrive in this mode.Show Less
Hi.. I'm facing a couple of funny problems...
I want to run my PSoC 5 as fast as possible, so I set the IMO to 48MHz and the PLL to 76MHz (the fastest it'll go with the error limits not exceeding 80MHz). The UART complains that the error in clock is too much. So I pulled down the IMO slower; the only possible setting is the slowest, i.e. 3MHz. so the first Q is
1. Is it ok to run the PLL this way? (3M input and 76M output?)
Then I added a pair of SAR ADCs, which now complain that the internal clock frequency is too high and can at most be 18MHz. I have selected external clocking and am providing 18M to it. (See attached). Now the only way to fix that is to slow my PLL down or use only IMO directly; thereby slowing the entire chip to a crawl.
2. What is the workaround?
Thanks in advance,
Abhijit KShow Less
I have a current project and suddenly the number of uset modules listed in the catalog has shrunk to only two. Any ideas?Show Less
mixed analog-digital scope http://www.cypress.com/?id=3312&conID=235
Wonderful project for the study of PSoC. I'm trying to figure out.
Found the problem:
1. Require () for triggerActive?16:0
327 +(triggerActive?16:0) // if no other triggers are active, trigger with bus count
2. Posted by hysteresis in triggers Comp_1 Comp_2 and for greater stability of the front.
There are questions:
3. 2-bit resolution ADC (figure1) - why?
4. There is a shift of channel 2 increases over time (figure2).
If possible, tell me the reason or solution.
sorry for the meaningless name of the theme
hi this is vishnu
in my project i am using two uarts . i have written recieve interrupt for one uart. how we can write another recieve interrupt for uart2?Show Less