PSoC™ 5, 3 & 1 Forum Discussions

Hi all,

New to the forum and PSoC Devices. I am also new to my current employer. I have inherited a project that has a CY8C24223A-24PVXI device fitted. I have some source code from a contractor the company has used. I was wondering how I can load the C code back onto the compiler (I have all the Cypress application softwarePSoC Designr 5.1 and the Programmer 3.13.3 ) and then maybe manipulate the C code to generate a new hex file. Not sure how to do this? Any help gratefully recieved.

Kind regards

Jeff

After Parallel DAC and Dithering techniques, the next trick to create four DAC outputs using a single DAC, the SC/CT blocks, an LUT and the DMA.

The four SC/CT blocks are configured as Track and Hold circuits whose inputs are connected to the VDAC8.  A four byte array in the RAM holds the values for the four DAC outputs. The DMA reads from this four byte array and writes to the DAC in sequence. An LUT component generates the trigger for the DMA and the Track and Hold circuits. The sequence goes like this.

DMA updates VDAC with the first value, LUT generates the strobe for the TrackAndHold1 and the output of the DAC is held on output1.
The LUT generates a trigger to the DMA which updates DAC with the second value. LUT generates a trigger to TrackAndHold2 and Output2 now has the 2nd DAC value.
This repeats for all the four DAC values and the cycle continues.

The refresh rate is chosen fast enough such that there is very little droop in the TrackAndHold outputs. Also, there is no CPU overhead as everything is taken care of by the DMA. The only overhead for the CPU is to update the RAM array with the desired DAC value. As the TrackAndHold has low output impedance, there is no need to buffer the outputs.

Hi all,

I am experiencing some troubles making RS485 communication through UART. I am using First Touch Kit and Ti ISO3086 driver. I am connecting the RE and DE short, and they are connected to Tx_E out of the UART. D of the driver is connected to the TX and R is connected to RX of the UART. The program code that I am using is quite simple.

test = UART_485_ReadRxData ();
        if (test !=0 )
        {
            UART_485_WriteTxData (test);
        }

I am missing something (probably in the configuration of the UART or in the firmware code). I have managed to make it send data (as a second device I am using RS485 to RS232 converter and Hyper Terminal), but can’t make it receive some data. The driver was configured as a Half Duplex. If I want to make it work as Full Duplex, how should I connect the output of the UART and the input of the driver? What should be the configuration of the UART in this case?

I will appreciate any help!

Thanks in advance!

With a handful of PSoC3 resources and an external capacitor, a Voltage controlled oscillator can be created.

Pin "Cint" is configured as both Digital and Analog pin with a drive mode Open Drain drives low. When output of Comparator is High, IDAC output is connected to the pin.  When comparator output is Low, the pin shorts to Ground.

IDAC – configured as a source – charges an external capacitor connected to "Cint". When the capacitor voltage crosses input voltage Vin, comparator output becomes low (comparator is set for inverted logic) and discharges the capacitor. As capacitor voltage becomes zero, the comparator output becomes high and IDAC starts charging the capacitor. The cycle continues and we get an oscillator whose frequency is inversely proportional to Vin.  The circuit has excellent “Period vs. Vin” linearity.

For a given input voltage, the combination of IDAC value and external capacitor determines the maximum Period (1/f) of the output.  We know that when a capacitor is charged using a constant current, the time taken to charge to a known voltage is

t = C * V / I

For example, if the maximum period value is desired to be 500uS for an input voltage of 2.5V, for an IDAC value of 1uA, the value of C can be calculated:

C = (500uSec * 1uA) / 2.5V = 200pF

Hi All,

I just read this blog post by Mark H and thought that it's a great idea to share it with everyone.

Remember way back when you were learning about voltage and current sources, you were told it was bad to put voltages sources in parallel and current sources in series.  These are good rules, but often a voltage source is not exactly and “ideal” voltage source.  Take the PSoC 3/5 VDACs.  At first glance they seem like a typical voltage source and you would never think about putting them in parallel.  If you look under the hood, you will find that this voltage source is really a current source with a resistor.  When the VDAC range is selected to be 1 volt, it is equivalent to an IDAC in the 256uA range with a 4K resistor connected between the output and Vss.

So you might say “so what?”  This means we can actually put two VDACs in parallel and not violate the law of parallel voltage sources.  In the diagram below you can see that two parallel VDACs in parallel really look like a single IDAC with double the current output with a 2K load to Vss.  The 2K resistor is the result of two 4K resistors in parallel.

If each of the VDACs (VDAC8_1 and VDAC8_2) generate a separate waveform and the VDAC outputs are connected, we simply get the average of those two signals.  Take a look at the scope image below where the two upper traces are the two individual VDAC output. The third signal on the bottom is the output of these two signals when the DACs are connected in parallel.

Just to have a bit more fun, do you remember when you learned about Fourier series?  I remember how cool I thought it was the first time we looked at the FFT of a square wave and learned the relationship of the harmonics to input square wave.  Looking at just the first four harmonics we get the equation below.

We then had to write a program to prove this and display it graphically.  With PSoC you can prove it just by connecting four VDAC8s in parallel.  As you can see in the image below, the upper four sine waves are averaged together to create the pseudo square at the bottom.  Wish I had a PSoC back in school about 30 years ago.

This is just a handy trick when you need to average two or more individual signals in hardware and don’t want to use any external components.

Hi,

please can you tell if there is an Appnote example about hooking PSoc1 to Ethernet network?  Particulary the software driver is of my interest. Thanks!

 HI,

We are developing a  project using PSoC, The project is nearly finished, but we would like know if we can use a bit more RAM for some furture expansion. We sould also like to know how much RAM is being used for stack and heap, (I mean it is ACTUALLY used, not being assigned for ). Any one has any idea how we can get the information.  I have this post to Cypress support already, hope some one has done this before. 

I know there are programs to trace stack usage but not sure it is aviable for PSOoC5 or G++ lite for ARM devices.

There is another way which is to fill the stack area with a spcial pattern and let the program run and excersise the possible combination and then check the pattern again -( this is not as good as the first one, but at least give some indication of usage.) I am reading the CodeSourcery manual and would like to know if some one has the experience to modify the startup code to do this

Thanks

I have PSoc Creator 1.0 Service Pack2 installed on my system and I have copied the freeRTOS folder in "C:\Program Files\Cypress\PSoC Creator" and when I open "FreeRTOS_Demo Workspace.cywrk"  from C:\Program Files\Cypress\PSoC Creator\FreeRTOSv7.0.2\Demo\CORTEX_CY8C5588_PSoC_Creator_GCC it tel me taht I should update some components but after accepting to update it shows me the below error:

Log: prj.M0171: A workspace is being opened in a newer version of this tool than it was last saved in. In order to preserve the ability to open the workspace in that older version of the tool an attmept was made to create a backup. This operation failed due to the following so making changes and saving may result in the inability to open this workspace in the older version of the tool. 'Could not find a part of the path 'C:\Program Files\Cypress\PSoC Creator\FreeRTOSv7.0.2\Demo\CORTEX_CY8C5588_PSoC_Creator_GCC\Backup\FreeRTOS_Demo Workspace.1.0_Beta_5.0.zip'.' This feature can be turned off from Tools/Options/Project Management/General/Auto-Backup Designs.
Error: gde.M0007: Save failed: (Access to the path 'C:\Program Files\Cypress\PSoC Creator\FreeRTOSv7.0.2\Demo\CORTEX_CY8C5588_PSoC_Creator_GCC\FreeRTOS_Demo.cydsn\TopDesign\TopDesign.cysch' is denied.).
Warning: prj.M0030: Unable to save the project file "C:\Program Files\Cypress\PSoC Creator\FreeRTOSv7.0.2\Demo\CORTEX_CY8C5588_PSoC_Creator_GCC\FreeRTOS_Demo.cydsn\FreeRTOS_Demo.cyprj": (Access to the path 'C:\Program Files\Cypress\PSoC Creator\FreeRTOSv7.0.2\Demo\CORTEX_CY8C5588_PSoC_Creator_GCC\FreeRTOS_Demo.cydsn\FreeRTOS_Demo.cyprj' is denied.). Address the given problem before the project can be saved.
Error: sdb.M0036: Component update log could not be updated.

----------------Components are updated successfully---------------

 

and after this when i want to CLEAN AND BUILD  it it shows me teh below warning:

Warning: prj.M0030: Unable to save the project file "C:\Program Files\Cypress\PSoC Creator\FreeRTOSv7.0.2\Demo\CORTEX_CY8C5588_PSoC_Creator_GCC\FreeRTOS_Demo.cydsn\FreeRTOS_Demo.cyprj": (Access to the path 'C:\Program Files\Cypress\PSoC Creator\FreeRTOSv7.0.2\Demo\CORTEX_CY8C5588_PSoC_Creator_GCC\FreeRTOS_Demo.cydsn\FreeRTOS_Demo.cyprj' is denied.). Address the given problem before the project can be saved.
Build failed - one or more files could not be saved.

I think I hsoudl modify the address in some files but I don't know which file

anybody can help?