PSoC™ 5, 3 & 1 Forum Discussions
Question: How can CPU/DMA read from a verilog component implemented in PLDs of UDB Blocks.
Answer: | There are no hardware registers associated with the PLD based verilog component which would store the values of the signals used inside the component. Hence the CPU/DMA cannot read directly from the component. One way to read from the component is to bring the required signals out through output pins and connect a status register to it. A simple example of a 3 bit counter is as follows. module Mod3Counter ( count, clock ); output [2:0] count; input clock; //`#start body` -- edit after this line, do not edit this line reg [2:0] count; always @(posedge clock) begin count <= count+1'd1; end // Your code goes here //`#end` -- edit above this line, do not edit this line Endmodule As it can be seen ‘count’ has been made an output signal. A status register should be connected to the ‘count’ terminal as shown below.
The CPU can read the counts by simply reading the status register. The counts can be transferred to another destination using DMA by setting the source address as the address of the status register. |
hi in PSoC1 what is the minimum voltage required by the PGA in order to amplify the signal.
if i am giving 0.01mv is it going to amplify this voltage?
Thanks and Regards
V.Vishnu Kumar
Show LessHi Folks,
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Is it possible to create a 24 bit ADC in psoc 5, if so how? In the same way can we use VHDL besides verilog to build our own components in PSOC 5.
I have a doubt regarding EMIF, can we interface a 16GB external memory to psoc 5 devices
Hi:
Using C51 Lib in Creator 1.0, printf() works as putchar() re-defined in main file.
But when re-define getchar() to implement scanf(), error happened:
*** ERROR L104: MULTIPLE PUBLIC DEFINITIONS
SYMBOL: GETCHAR
MODULE: C:\PROGRAM FILES\CYPRESS\PSOC CREATOR\1.0\PSOC CREATOR\IMPORT\KEIL\PK51\8.16\C51\LIB\C51L.LIB (GETCHAR)
DEFINED: E:\1_WaveDAC8_SimpleSine.cydsn\DP8051_Keil_816\Debug\main.OBJ (MAIN)
Any idea about that ?
Thanks very much.
Show Lesshi.
i am trying to create ADC SAR in scanning mode in its full speed and i am having some problems .
the basic idea is to take the analog mux and lut link them to the dma so that every channel will go into differnt buffers so that i have an array of variables that each one represents one channel of measure.
i want to make one swift of all the channels and stop. then start again in software.
is it possiable?
i was able to to something but the channels affect one another.
thanks .
Show LessOne of the more powerful aspects of PSoC 3 and PSoC 5 is the ability to use components that encapsulate both hardware and software functionality. Cypress provides a large library of the most common components that you might need (I2C, UART, DAC), but there is no end to the possible components that PSoC 3 and PSoC 5 can support. The Creator platform allows you to develop and use your own components using the same methodology as Cypress engineers.
There are 3 levels of components that a user might want to develop:
- Schematic Component
- Verilog Component
- Datapath Component
Each level gets progressively more involved and more powerful. A schematic based component provides a hierarchical schematic capability. Here you can combine any of the components in the current library and also encapsulate the APIs that go with that combination. With a Verilog based component you have the ability to pull in more complex unique digital content and take direct advantage of the PLDs built into PSoC 3 and 5. The capability to do either Schematic or Verilog based components is in Creator today. The third level, datapath based components, adds to a Verilog component the usage of the datapath resources in PSoC 3 and 5. With datapaths you can create denser designs and more flexibily communicate between your hardware component and the CPU.
In order to get you started on the right track, several training classes are developed that include:
- Video
- Slides
- Example Projects
They are all posted on the Cypress website under the Design Support tab, then Technical Training, then On-Demand Training, or you can skip directly there with the following links:
- PSoC Creator 110: Schematic Components
- PSoC Creator 111: Component Parameters
- PSoC Creator 112: Introduction to Component API Generation
- PSoC Creator 113: PLD Based Verilog Components
I am trying to select a part with a 16 bit PWM, 10 bit ADC, and a UART. How do I determine the resources necessary to select the part and where do I find a list of what is Pin for Pin so I can see future migration options.
Thanks!
Show LessPSoC1 Power Savings Using Sleep Mode
The importance of system power consumption management cannot be overstated. The use of PSoC’s sleep mode is a simple and efficient way to reduce overall current draw without limiting the functionality. Significant power savings can be realized if attention is given to the proper entry, use, and exit of sleep mode. When implemented in conjunction with other power-saving features and techniques, sleep mode can be extremely effective in reducing the overall power consumption in a PSoC-based design. Below is an example of a technique to reduce the power consumption in sleep mode by disabling PSoC features that may remain active when the SLEEP bit is set.
Disable CT/SC Blocks
The continuous time (CT) blocks are powered down individually with a write to each ACBxxCRy or ACExxCRy register corresponding to the block’s column. The switch capacitor (SC) blocks are similarly controlled by the ASCxxCRy or ASDxxCRy registers. The example below shows how to disable the CT and SC blocks for column zero.
ACB00CR2 &= 0xfc; // Disable CT Block
ASC10CR3 &= 0xfc; // Disable typeC SC block
ASD20CR3 &= 0xfc; // Disable typeD SC block
The CT blocks can remain in operation because they do not require a clock source. However, the SC blocks do not operate because there is no clock source for the switches.
Application Note AN47310 – PSoC1 Power Savings Using Sleep Mode provides an overview of PSoC1 sleep mode basics and information on power-saving methods, and other sleep related considerations.
Show LessIt is mentioned in the data sheet that PSOC5 supports AMBA, so it is probably possible to connect a parallel RAM to the chip. Can I expand system RAM to the external chip to get, for example 8MBytes RAM? I was not able to find any sample projects using this feature and there is no application note about this. Thank you!
Show Less