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PSoC™ 5, 3 & 1 Forum Discussions

Anonymous
PSoC™ 5, 3 & 1
Question: How can CPU/DMA read from a verilog component implemented in PLDs of UDB Blocks.                                             Answer:  There ... Show More
Anonymous
PSoC™ 5, 3 & 1
hi in PSoC1 what is the minimum voltage required by the PGA in order to amplify the signal.    if i am giving 0.01mv is it going to amplify this volta... Show More
Anonymous
PSoC™ 5, 3 & 1
Hi Folks,    Have you noticed the follow button on the left side on the Cypress Forum webpage? Well, Cypress is on Facebook and it is probably time to... Show More
Anonymous
PSoC™ 5, 3 & 1
Is it possible to create a 24 bit ADC in psoc 5, if so how? In the same way can we use VHDL besides verilog to build our own components in PSOC 5.    ... Show More
Anonymous
PSoC™ 5, 3 & 1
Hi:    Using C51 Lib in Creator 1.0, printf() works as putchar() re-defined in main file.    But when re-define getchar() to implement scanf(), error ... Show More
ezbe_290006
PSoC™ 5, 3 & 1
hi.         i am trying to create ADC SAR in scanning mode in its full speed and i am having some problems .    the basic idea is to take the analog m... Show More
Anonymous
PSoC™ 5, 3 & 1
One of the more powerful aspects of PSoC 3 and PSoC 5 is the ability to use components that encapsulate both hardware and software functionality.  Cyp... Show More
Anonymous
PSoC™ 5, 3 & 1
I am trying to select a part with a 16 bit PWM, 10 bit ADC, and a UART.  How do I determine the resources necessary to select the part and where do I ... Show More
Anonymous
PSoC™ 5, 3 & 1
 PSoC1 Power Savings Using Sleep Mode    The importance of system power consumption management cannot be overstated. The use of PSoC’s sleep mode is a... Show More
Anonymous
PSoC™ 5, 3 & 1
It is mentioned in the data sheet that PSOC5 supports AMBA, so it is probably possible to connect a parallel RAM to the chip. Can I expand system RAM ... Show More
Forum Information

PSoC™ 5, 3 & 1

The PSoC™ 5LP, PSoC 2 and PSoC 1 Forum discusses - 24-bit Digital Filter Block (DFB), 24 UDBs, DMA controller and integrating AFE, digital logic with user interface ICs with an Arm Cortex-M3 CPU solutions.