I just noticed in datasheet, there are two types of datapath, one in UDB, the other in DFB. Is that correct? Obviously the two 'types' datapath are not the same architecture, different ALU input selection, RAM size, output pipeline...and so on.
It seems the datapath configure tool is to configure the UDB datapath only, is that correct? I can not find any tool to help customized design on DFB datapath.
My application has a stream of digital values being captured by a FIFO (http://www.cypress.com/?rID=46730). The number of data points sent by my target is 25,344 bytes. I have been able to estabilish a 2-D array in memory of the PSoC 5 device that works.
I am concerned that the DMA might not be able to directly transfer such a large chunk of data. I understand that it has some kind of counter limit?
Does anyone have any suggestions on how to go about this?
I'm new to PSoC family,previously i used Freescale and Microchip controller for programming.
In PSoC I want to do multichannel ADC conversion and i want to do each 3 ADC channel conversion within the ISR of timer for 1msec.For design this i used one 9 channel multiplexer and 1 delta sigma ADC.I also used 1 timer.In codding i want to do generate a timer interrupt for every 1msec and in the ISR of Timer i want to do ADC conversion and some other calculation.
Can you please suggent me which type of timer i have to use and how to generate 1msec of delay.
Hi, I'm just starting to think about the video now, and was wondering if there were any guidelines? E.g. about how long, whether it should focus on the development process or the final result, whether we can get outside help with producing it, and whether Matt Damon would be available to play me, since I'm not very photogenic.Show Less
I was going to use Basic Design to learn about the Debugger. I loaded it and tried to do a build. The errors indicate that the (hardware?) is set to 5.5v on the Vddio0-3 pins (they were so I fixed the jumper pins on the -001 kit board) and I selected 3.3v with the slide switch. HOWEVER, I still get that set of errors when I do a clean and build for Basic Design.
What did I forget or miss?
Tim MShow Less
Hi, just wanted to alert any potential prototyping area users that the holes are NOT isolated from each other! See page 40 of the dev board manual for the pattern (it's the faint blue lines between the holes).
To scan each CapSense element, the scanning time can be divided into three time periods pre-scan, post
scan and hardware time for scanning. The hardware time for scanning does not require CPU and the CPU can be
shut off during this time to save power. After the hardware scanning of button an interrupt will be generated and the
CPU wakes up on this interrupt.
Call the API to scan all the sensors “CapSense_ScanEnabledWidgets()”, it will set the CapSense
parameters for the button, starts the hardware scan and returns the main function. Next line of code in the main loop
is API “CyPmAltAct()”,which puts the device into alternative active mode. Alternative active mode by default
is configured such that it will have all the blocks running/disabled same as in the active state but CPU is shut down.
When the hardware finishes the scanning a button it generates an interrupt and the CPU wakes up and it starts
executing the ISR code which is post scan time.
This is one of the many benefits of PSoC 3 CapSense that is based on the hardware universal digital block implementation. Please stay tuned as we are exploring more...Show Less
With no external driver required, the “Segment LCD Driver” is the first user module that truly enables the easy-to-use and command-and-control development tool for low cost LCD segment direct drive with PSoC 1 with no external components required. This user module (SLCD) applies to all the PSoC 1 families.
Here is the link to applicate note on this topic:Show Less
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