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 `include "cypress.v"

`ifdef counter4bit_ALREADY_INCLUDED

`else

`define counter4bit_ALREADY_INCLUDED

//`#end` -- edit above this line, do not edit this line

//`#start body` -- edit after this line, do not edit this line

module counter4bit (

    Count_Out,

    Min,

    Max,

    Load_Val,

Clock,

Load,

Roll_Enable,

Reset

);

output [3:0] Count_Out;

output  Min;

output  Max;

input   Clock;

input   Load;

input   Roll_Enable;

    input   [3:0] Load_Val;

input   Reset;

parameter Up_Down = 1;

    reg     [3:0] Count_Out; // current count value

    reg     Min; // min output

    reg     Max; // max output

    // assign output lines to registers

    // whatever happens to the counter, set min and max accordingly

    always @(Count_Out)

    begin

        Min=(Count_Out==0);

        Max=(Count_Out==15);

    end

    always @ (posedge Clock or negedge Reset)

    begin

        // handle async reset

        if (Reset==0)

            Count_Out <= 4'b000;

        else 

        // when load is high durign a clock puilse, load the value (and don't count)

        if (Load)

        begin

            Count_Out<=Load_Val;       

        end

        // count in the right direction

        // and check for possible (and allowed) rollover

        else if (Up_Down)

            if (Roll_Enable || Count_Out!=15)

                Count_Out <= Count_Out+1;

            else

            begin

            end

        else

            if (Roll_Enable || Count_Out!=0)

                Count_Out <= Count_Out-1;

            else

            begin

            end

    end

endmodule

//`#end` -- edit above this line, do not edit this line

//`#start footer` -- edit after this line, do not edit this line

`endif

//`#end` -- edit above this line, do not edit this line

 `include "cypress.v"

//`#end` -- edit above this line, do not edit this line

// Generated on 12/17/2012 at 13:40

// Component: FourBitCounter

module FourBitCounter (

output [3:0] Count_out,

output  Max,

output  Min,

input   Clock,

input   Load,

input  [3:0] Load_val,

input   Reset,

input   Roll_enable

);

parameter Max_Count = 0;

parameter Min_Count = 0;

parameter UPdown = 0;

//`#start body` -- edit after this line, do not edit this line

reg[3:0] count;

assign count = Count_out;

always@(negedge Reset) //asynch reset

begin

count=0;

end

always @(posedge Clock)

begin

if (Load == 1) begin //Check for load condition

count = Load_Val;

end

if  (UPdown==0) begin //check if counting down

if (Roll_enable == 1) begin //check if roll and count regardless

count = count - 1;

end

else begin

if (count > Min_Count)  begin

count = count - 1; //if greater than Min, count 

end

end

end

else begin //counting up is the other option

if (Roll_enable == 1) begin //check if roll and count regardless

count = count + 1;

end

else begin

if (count < Man_Count)  begin

count = count + 1; //if less than Man, count 

end

end

end

end

always @(posedge Clock) begin //Check for Max condition

if (count >= Max_Count) begin

Max = 1;

end

else begin 

Max = 0;

end

end

always @(posedge Clock) begin //Check for Min condition

if (count =< Min_Count) begin

Min = 1;

end

else begin 

Min = 0;

end

end

//        Your code goes here

//`#end` -- edit above this line, do not edit this line

endmodule

//`#start footer` -- edit after this line, do not edit this line

//`#end` -- edit above this line, do not edit this line

 `include "cypress.v"

module Count4Bit_v1_0(

Clock,

Load,

Roll_enable,

Load_val,

Reset,

Count_out,

Min,

Max

);

parameter CountUp = 1;

input Clock;

input Load;

// input Up_down;

input Roll_enable;

input Load_val;

input Reset;

output Count_out;

output Min;

output Max;

// reg [3:0]Load_Reg;

reg [3:0]Count_out;

reg Load_Flag;

wire [3:0]Load_val;

//`#start body` -- edit after this line, do not edit this line

assign Min = (Count_out == 4'h0);

assign Max = (Count_out == 4'hf);

/* */

always @(posedge Clock or posedge Load)

if(Load)

begin

Load_Flag <= 1'b1;

end

else begin

Load_Flag <= 1'b0;

end

/* */

always @(posedge Clock or negedge Reset)

if (~Reset)

begin

Count_out <= 0;

end

else begin

if(Load_Flag)

begin

Count_out <= Load_val;

end

else

begin

Count_out <= CountUp?(Count_out[3:0]+{0,0,0,Roll_enable | ~Max}):(Count_out[3:0]-{0,0,0,Roll_enable | ~Min});

end

end

//`#end` -- edit above this line, do not edit this line

endmodule

//`#start footer` -- edit after this line, do not edit this line

//`#end` -- edit above this line, do not edit this line

 `define UP 0

`define DOWN 0

module up_down_counter(

input clock,

input reset,

input load,

input roll_enable,

input[3:0] load_val,

output reg[3:0] count_out,

output max,

output min

);

parameter up_down = 0;

wire halt = (!roll_enable) & (((count_out == 4'h0) & up_down) | ((count_out == 4'hF) & !up_down));

assign max = (count_out == 4'hF);

assign min = (count_out == 4'h0); 

always@(posedge clock or negedge reset) begin

if(!reset)

count_out <= 4'b0;

else if(load)

count_out <= load_val;

else if(~halt)

if(up_down == `UP)

count_out <= count_out + 1'b1;

else

count_out <= count_out - 1'b1;

end

endmodule