PSoC™ 5, 3 & 1 Forum Discussions

 Hello PSoC world,

How to create a differentiator using a SC block module ? (Without any external passive components) - This would help me in eliminating the glitches & delays I encounter now when I go for a combo design with external RC network. 

Please attach application notes, howsoever old it is 🙂 

Regards,

RAM

Dear Fourm,

Im attempting to transfer with the dma filter results from the holding register directly to a 8 bit control register.  I have been using the dma wizard to produce the needed code for configuring the dma.  When compiling Im getting a error Im not sure what to do with. 

Here is what the wizard is producing.

/* Variable declarations for FILT_DONE_DMA_LO */
/* Move these variable declarations to the top of the function */
uint8 FILT_DONE_DMA_LO_Chan;
uint8 FILT_DONE_DMA_LO_TD[1];

/* DMA Configuration for FILT_DONE_DMA_LO */
#define FILT_DONE_DMA_LO_BYTES_PER_BURST 1
#define FILT_DONE_DMA_LO_REQUEST_PER_BURST 1
#define FILT_DONE_DMA_LO_SRC_BASE (CYDEV_PERIPH_BASE)
#define FILT_DONE_DMA_LO_DST_BASE (CYDEV_PERIPH_BASE)
FILT_DONE_DMA_LO_Chan = FILT_DONE_DMA_LO_DmaInitialize(    FILT_DONE_DMA_LO_BYTES_PER_BURST,
                                                        FILT_DONE_DMA_LO_REQUEST_PER_BURST,
                                                        HI16(FILT_DONE_DMA_LO_SRC_BASE),
                                                        HI16(FILT_DONE_DMA_LO_DST_BASE));
FILT_DONE_DMA_LO_TD[0] = CyDmaTdAllocate();

CyDmaTdSetConfiguration(    FILT_DONE_DMA_LO_TD[0],
                            1,
                            DMA_INVALID_TD,
                            0);
                           
CyDmaTdSetAddress(    FILT_DONE_DMA_LO_TD[0],
                    LO16((uint32)Filter_1_HOLDA_PTR),
                    LO16((uint32)CTRL_REG_FILT_LO_Control_PTR));
                   
CyDmaChSetInitialTd(FILT_DONE_DMA_LO_Chan, FILT_DONE_DMA_LO_TD[0]);
CyDmaChEnable(FILT_DONE_DMA_LO_Chan, 1);

The error message is

prj.M0120:'CTRL_REG_FILT_LO_Sync_ctrl_reg__CONTROL_REG' undeclared (first use in this function)

The other dmas I have done I have not had a issue like this where the var is undeclared. 

#define CTRL_REG_SET_CURRENT_LO_Control_PTR    (  (reg8 *) CTRL_REG_SET_CURRENT_LO_Sync_ctrl_reg__CONTROL_REG )

Creator 2.2.0.293 and running cy8ckit-050 with a psoc5lp part.

Thanks for the help.

Matt

 Hi all

Please is possible make simple multiplier on datapath ? (example: two input 8bit * 8bit = 16bit output)

On the verilog is simple but very big UDB consumtion.

Many thanks help and example.

Kamil

The data path FIFOs in the PSoC3/5 UDB can be used as a single buffer; rather than a FIFO of depth 4. In this case, what happens is that, the FIFO read and the write pointers does not increment/decrement and will create an apparent illusion that only a single register exist. 

When the FIFO is used as a single buffer, we shall not worry about the status signals. We can read and write data from and in to the FIFOs at our will. We should also be cautious about the fact that FIFO can be overwritten and hence will require a proper read signal (which should all be taken care, inside the verilog code) before the next data could be written.

To configure the FIFO in a single buffer mode, we need to set the lower 2 bits in the Auxillary control register. It is advised that when ever we modify the auxillary control registers, we should do it with the interrupts disabled. Hence, we can do this change inside the critical region. The procedure to enter the critical region and modify the auxillary control register is given below.

AUX Control Register :

Counter Start - This will start the inbuilt 7 bit counter.

Interrupt enable-- The status register shall sometimes be used to generate interrupts. for ex, we can generate an interrupt on every FIFO load, so that the CPU can read the contents. This can be done by using the status register and by setting the bit4 of the AUX CTL register.

 FIFO 1 and 0 LVL bit setting will enable the half or full bus status. By default the value is 0 and when the LVL is 0, the two issued bus signals are "Not empty" and "half full"  for the output configured FIFO; while it will be " Not Full" and "Half empty" for an input configured FIFO. Whne the LVL is set to 1, the 2 BUS signals will change from half full and half empty to "full" and "empty".

This means that the FIFO status signals will be for a depth of 4 rather than 2.

The CLR register bits, when set, will make sure that the FIFO is used in the single buffer mode and there is no dependancy on the status signals.

To enter the critical region and modify the contents of the registers, follow the procedure shown below in the code.

#define MYCOUNT7_AUX_CTL (* (reg8 *) MyInstance__CONTROL_AUX_CTL_REG)

uint8 interruptState;

/* Enter critical section */

interruptState = CyEnterCriticalSection();

/* Set the Count Start bit */

MYCOUNT7_AUX_CTL |= (0x03);

/* Exit critical section */

CyExitCriticalSection(interruptState);

Happy Designing,

Rahul ram

Friends,

Can I connect directly to external device from Tx and Rx at J13 ? For example I wanna send 0x01 to another device from PSoC 1?

Then send command to Tx with UART_CPutString("My command");

what's the different between UART_CPutString and UART_PutString

thank you

 Hi all

Please info how max clock speed ISR module ?

Im testing interrupt with ISR module with Clock module and maximal frequency is aprox. 3-4 kHz. How to use ISR with bigger frequency ?

Thanks Info

Kamil