PSoC™ 5, 3 & 1 Forum Discussions
Hi Guys,
Could you please let me know if UDB logic configuration can be preserve or not when a software or watchdog reset in PSOC parts? thanks.
Show LessHi Guys,
Could you please llet me know if UDB logic configuration can be preserve or not when a software or watchdog reset in PSOC parts? thanks.
Show LessAre you running out of counters/Timer/PWMs in the PSoC UDB due to the Datapath resources being utilized? Thes countcell counters will come in to a rescue then. These counters use the control cells in the UDB, and hence we have a privilege to use 24 of them in PSoC3/5LP architecture. The control cells shall either be used as a control register or as a 7 bit counter lilke this.
Remember that these are 7 bit counters that counts down and not 8 bits.
To get this counter up and running, we need to instantiate the following code,
cy_psoc5_count7
#(.cy_init_value(7'b1111111),.cy_alt_mode(`TRUE),.cy_period(7'b1111111),.cy_route_ld(`FALSE),.cy_route_en(`TRUE))
counter(
/* input */.clock(clk),
/* input */.reset(reset),
/* input */.load(1'b0),
/* input */.enable(enable),
/* output [06:00] */.count(count2),
/* output */.tc(tc1)
);
Just hook up the appropriate inputs to this module and get the counter running. A very important point to remember here is that, to enable this counter, we need to enable the counter both in the hardware and also in the software. In hardware, the enabling happens, when the appropriate enable signal is hooked up in the module above. To enable the counter in the software, we have to set the 5th bit in the Auxiliary control register. To do that, open the "cyfitter.h" and figure out the appropriate Auxiliary register for that instance and write a 1 to the 5th bit. The register will look like the one shown below
countcell_1_cnt7_counter__CONTROL_AUX_CTL_REG |= 0x20;
This will enable the counter in software.
Happy designing,
Rahul ram
Show LessHej
I cant get my LCD screen to work at all. I have followed the example in the pdf file.
http://www.cypress.com/?docID=33243
set it up by trying to use port 6 or port 0 but it will still not work. the program code is copied directly from the example and doesnt give any errors.
I am using a 1k potmeter for the display.
have moved the jumper so i get a 5V output from VDD.
when i build nothing happens on the screen. when build is finished i unplug the psoc 3 from the pc and plug it in again, nothing happens.
what could be the problem?
hope you guys can help
regards Jason
Show LessHello Forum,
What is the max. operating freq. of 3 op-amp instrumentation amplifier user module in PSoC 1 ? Does the use of an SC block (for conversion gain, as they call it) reduce speed of the incoming pulse ?
Any working code which has only the 3 op-amp instrumentation amplifier with settings that would enable it to operate at very high slew rate would be very helpful.
RAM
Show LessHi every One,
In my previous post, i had mentioned the existance of Count7 counters in PSoC UDB. I would like to add more on that. There is a terminal count signal that is coming out from the count7 counter. This terminal count is available in 2 forms, one the unregistered version and the other one is the registered version.
To select between the two, we will just have to use the cy_alt_mode. When the cy_alt_mode is " False" , the terminal count signal coming out is registered or delayed by a clock cycle. This means that we will get the terminal count signal, when the count reaches the "cy_period_value" , 127 in the default case.
When the cy_alt_mode is made "TRUE", the terminal count signal is issued when the count reaches the value "Zero".
happy designing,
Rahul Ram.
Show Less