PSoC™ 5, 3 & 1 Forum Discussions

Hello Friends I have a problem whith RX interrupt, I only want to read when I have a data, but the interruption comes once and then, never comes to interrupt again, I attach my code 

I'm using the control regsister "DmaMsbReg" as the destination of a DMA transfer.  My custom component (MyOverlay) uses the value of this register on lines 251, 253 and 255 of MyOverlay.v.  However, the register is being removed from cyfitter.h.  Why?  It appears in cyfitter.h as the following:

/* DmaMsbReg */

#define DmaMsbReg_Sync_ctrl_reg__REMOVED 1u

Hi,

I am facing the following problem:

I want to create  boot loader and bootloadable project. But i am not seeing the advance settings in creator 3.2. How i can do this?

I attached the pic for better understanding of my problem.

Looking forward for your replies.

Regards

Awais

Hello,

I have already read "Getting started with CapSense" and the "PSoC3 and PSoC5LP CapSense Design Guide" but I still have a question regarding how CapSense works. In the design guide you will find figure 2-3 CapSense CSD Block Diagramm. For example I start scanning whether Button1 is pressed or not. CMOD is charged via SW3 and the source current. If the voltage equals a reference, the sigma delta converter opens SW3. The converter counts the ticks, how long SW3 is closed. From the amount of ticks you can say if the button is pressed or not.

What I don't understand is SW2 and SW1. I started the scanning and SW3 is open since CMOD is charged. Then SW1 and SW2 are opening and closing alternatively. Lets say the button is pressed and SW1 is closed and so SW2 is open. Cx is discharging CMOD depending on the capacitance of  Cx. Then SW1 and SW2 change states so Cx is being discharged. And this will repeat several times.

Is CMOD charged completely again in one cycle, so if SW1 closes again, SW3 will be open or can it happen, that when SW1 is closed, SW3 is closed as well?

Best regards.

Nice to meet you.

I am troubled now unexpected CPU reset.

Frequency with which it occurs is about once per hour.

It uses the watchdog timer,but is it not the cause.

In the main routine just to be sure, I'm writing to...

main()

{

 CyVdLvDigitDisable();
 CyVdLvAnalogDisable();
 CyVdHvAnalogDisable();

It is quite troubled, but there is no place to come to mind in the other.

I think there are cases where the same thing is happening in other user?

Type name of the CPU,CY8C5868AXI-LP035(PSOC5LP).

Development envrionment PSoC Creator 2.2 SP1

Use external clock 24MHz OSC-IC.

Hi,

I have a SPI slave component (obviously talking to some master...) which is part of a command interface.
The slave normally has less data than commands received...

SPI(UDB) full duplex slave has software buffers rx&tx enabled (size=64)

My simple question is basically: how do i define the standard reply data when no data is available to transfer from slave to master.
I would like to define txdata = 0x00 by default when no data is available to transfer to master. In my communication language this is a NOP.

(yes: i can do counting incoming bytes and making sure the tx-buffer is always filled to same amount...)

isn't there an elegant solution based on bufferEmpty of FIFOempty status?
status now: i see repeats of 'earlier' data from fifo of txbuffer...

any help is welcome ...

I have a project with a PSoC 5LP interfacing with both 5V and 3.3V external components.  

Is there a way to have two different output pins connected to a single digital line, one with 5V and another at 3.3V levels?

Or do I need to level shift outside of the chip?

--
Dario