PSoC™ 5, 3 & 1 Forum Discussions
Dear Sir,
for the datasheet Pin description, How can I know the I/O Pin is UART/SPI/PWM or GPIO interface?
any more pin description for I/O port? thanks.
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How long would a voltage have to be below the detection threshold to trigger an interrupt?
Hello. I've been beating my head trying to make this work. PSoC 3 processor, ADC to DMA to memory. Everything seems set up right but the DMA result memory location never gets the value. If I read the ADC directly I get a good value, so the ADC is working. The ADC interrupt is firing because I can breakpoint it there, and I can see that the ADC_convDone flag is set.
I've gone round and round with the documentation and think everything is set up right. But the DMA screens in Creator 4.4 do not exactly align with the documentation.
The one thing I cannot find is exactly how to set up the TD for my scenario. I have the ADC converting continuously, and the TD is set up as: Endian=off, trq=off, nrq=off, length=1, source ADC_DEC_SAMP_PTR, Inc=off, dest=memory value, Auto Next=off, and Next Td=End.
I have tried Auto Next=on and Next Td=0, but that does not change anything and I don't think it is right anyway.
So here are my setup values:
/* Defines for AzDma */
#define AzDma_BYTES_PER_BURST 1
#define AzDma_REQUEST_PER_BURST 1
#define AzDma_SRC_BASE (CYDEV_PERIPH_BASE)
#define AzDma_DST_BASE (CYDEV_SRAM_BASE)
/* Variable declarations for AzDma */
/* Move these variable declarations to the top of the function */
uint8 AzDma_Chan;
uint8 AzDma_TD[1];
/* DMA Configuration for AzDma */
AzDma_Chan = AzDma_DmaInitialize (AzDma_BYTES_PER_BURST, AzDma_REQUEST_PER_BURST,
HI16 (AzDma_SRC_BASE), HI16 (AzDma_DST_BASE));
AzDma_TD[0] = CyDmaTdAllocate ();
CyDmaTdSetConfiguration (AzDma_TD[0], 1, CY_DMA_DISABLE_TD, 0);
CyDmaTdSetAddress (AzDma_TD[0], LO16 ((uint32)ADC_DEC_SAMP_PTR), LO16 ((uint32)AdRes.Az));
CyDmaChSetInitialTd (AzDma_Chan, AzDma_TD[0]);
CyDmaChEnable (AzDma_Chan, 1);
What I want is for the memory location to get overwritten with each conversion - for now.
Thanks for any insight, Russ
Hi,
attached is a simple project to test the DMA inter-spoke performance between SRAM and UDB (SPI) block.
For a MASTER_CLK = BUS_CLK = 78MHz obtained results, measured DMA data transfer time (t_DMA_DONE - t_DMA_TRIGGER), vs. expected are:
- transfer 1 * 16bit: 146 ns, calculation: Nbursts = 1, InterSpoke transfer = Nbursts + 7 = 8 (102 ns)
- transfer 2 * 16bit: 250 ns, calculation: Nbursts = 2, InterSpoke transfer = Nbursts + 7 = 9 (115 ns)
- transfer 4 * 16bit: 457 ns, calculation: Nbursts = 4, InterSpoke transfer = Nbursts + 7 = 11 (141 ns)
Can anybody advise how to reach the speed as specified in the data-sheet?
This particular program has main loop doing nothing, in real example DMA arbiter priority was raised against the CPU however no significant effect has been observed.
Kind regards,
Uros
Hi,
I use ADC_SAR but I can't find how can I get the time between samples. Maybe someone can help?
EDITED:
Hello @EvPa_264126 ,
I have used your response from this link, as a start for my firmware interfacing to the ESP-8266 with PSOC5 LP.
But I am having an issue with the WaitText() function that has been used.
The firmware doesn't 'return 1' even when the string response is received properly from the ESP (checked the UART log) and only acts as a delay for the amount of time that is specified.
I would really appreciate it if you review the attached firmware and let me know what could be the issue.
Regards,
Yash