PSoC™ 5, 3 & 1

Hey all,

I'm looking into interfacing a PSoC5LP to a bit of a strange I2C Master.  Rather than being designed to run on a bus, I have to interface using SDA/SCL and an INT pin in a "point to point" configuration.  The idea is easy enough, it gives a edge on the INT line, I catch it with the PSoC, and read the 9 data bytes that it sends, but there's a twist. 

The catch is this device does not send an address, just the raw data bytes.  How can I adjust the SI2C to account for this?  I see I can use either Software/Hardware address decoding.  Hardware is probably out of the question since there's just no address at all.

This leaves me with software decoding, in which case it seems like modifying the ISR in SI2C_INT.c to just drop bytes immediately into the buffer rather than doing a check on the address might work.  Maybe some custom code placed in the SI2C_SW_ADDR_COMPARE_interruptStart code block in the ISR?  I could maybe set the "expected address" to something that should never occur as the first byte received (would need to see if this is possible, it only has 1 bit of data, the rest are "Reserved", so maybe they'll read all 0?  That would make it easy.) so it will drop into the address compare where I can drop my custom code to place the data in the receive buffer rather than use it as an address?

An easier option after looking further may be just to use the SI2C_ISR_EntryCallback(); and have it perform essentially a modified version of the stock Slave I2C code.

I'd be interested if anyone out there had any better options, maybe even something that just works in hardware?

Thanks!

I'm making improvements to my custom Term component.

I've got a modest work-around to determine if the host port is open.  I'd like to improve upon that.  

The goal:  Quickly determine if the Host port is open and ready to comm or if the host port is closed and DO NOT try to transmit.

Note: USBUART_CDCIsReady() will not work in this instance since it will always return 'not ready' if the Tx buffer is full OR if the HOST port is NOT opened.

I've gone through the datasheet, the USBUART component source code, and made some experimental code.  All to no luck.

Is there an API or Global variable that indicates whether the Host port is open?

Thanks in advance for your help and suggestions.

Hey all,

I'm trying to track down the cause of some PSoC5LP firmware running into the default interrupt with errno==ENOMEM.

The only way I've been able to reproduce it is to power cycle the PSoC quickly enough after powerup to catch it, and even then I've only been able to get it to occur maybe once every 50 or so cycles.  This makes using the debugger to track it down basically impossible from what I can tell.  It almost seems like it might be occurring when the PSoC is undervolted due to very quick loss and re-application of main power, so some "undefined behavior" might be occurring.  I know PIC MCUs I've worked with have a "Brownout Reset" function to automatically put the MCU into reset when VDD falls beneath a certain configurable voltage.  Does PSoC5LP have anything comparable?

I am running some BIT test on bootup in this firmware and *suspect* it occurs when I manage to power cycle/brownout the system while it is in progress of running these tests.  Specifically, I am running an SRAM March Test, a Stack March Test, and a Flash ECC Test on bootup.  The code for all these tests was taken from the examples in AN78175 (I made a thread about it months ago, actually: https://community.infineon.com/t5/PSoC-5-3-1/PSoC5LP-Using-SRAM-test-functions-from-AN78175/m-p/283692#M45177).

Right now when I manage to trigger the problem and enter the trap ISR for ENOMEM, I simply have it infinitely loop and blink an LED.  I wonder if it would be worth it to try and hunt the exact error cause down.  My other thought is that this occurs so infrequently and might be unavoidable enough, to just perform a software reset in the handler and call it a day?

I'd love a second or third opinion on maybe how I should track this down/handle it.

Thanks!

We have purchased the above IC from one of the open source as there were huge leadtime.

The IC snapshot is attached.

The IC part number/Body mark is CY8C3246AXI - 138 but in PsOC programmer it detects as CY8C3246AXI - 131. So we are unable to load the hex file of the program.

Can you help us?

Hi there,

In my project(program in attached file), I am using a MPU6050 for selfbalancing purposes. I got the raw MPU data, processed it, and obtained an angle. However, when I push the device, it returns a 'noise value' as shown below:

The angle of the MPU6050 is :0 deg
The angle of the MPU6050 is :0 deg
The angle of the MPU6050 is :0 deg
The angle of the MPU6050 is :-62 deg
The angle of the MPU6050 is :21 deg
The angle of the MPU6050 is :1 deg
The angle of the MPU6050 is :1 deg
The angle of the MPU6050 is :0 deg
The angle of the MPU6050 is :0 deg
The angle of the MPU6050 is :0 deg
The angle of the MPU6050 is :0 deg

Usually a kalman filter is used for this (I think), but I don't know how to do this/I don't understand it. Does anyone know how to do this?

Thank you and have a nice day.

Dear community,

This post is quite similar to one I previously posted (sorry for that) however I am more interested in how the PSoC5lp I2C slave works under the API functions.

Currently I have a raspberry pi I2C master reading 16-bit ADC data from a PSoC5lp (CY8KIT-059). I have set the ADC conversion rate to 2000 samples/second and the I2C bus frequency to 400 bits/second. Thus, for only one slave, the I2C bus is running more than fast enough to read the 2000 samples/second in time and I believe this is fine. My issue is that I believe the raspberry pi master is coming back to the PSoC5lp I2C slave before I2C slave buffer has had time to update to the next ADC sample. See I2C_data_duplicates.jpg attachment (it looks like a valid EMG signal which is what the ADC is sampling), however the signal is over sampled (I am tensing my bicep for 3 seconds and thus there should be approximately 6000 samples in each burst). I2C_data_duplicates_zoom.jpg shows that for each sample there are around 3 or 4 consecutive duplicate samples with approx. 25000 samples in a burst. Thus, post-processing I decided to write some code to remove consecutive duplicates (I2C_data_no_duplicates.jpg/ I2C_data_no_duplicates_zoom.jpg). When removing the duplicates, the approx. number of samples in a burst reduces to 6581 (which when divided by 3 seconds) is about 2193.67 samples/second. Removing duplicates, the sample rate is close to what is set in PSoC creator. Removing duplicates is not a robust solution of course - as sometimes a duplicate sample might actually be correct.

So my question is - the way that PSoC sets up the I2C slave component, is it possible for the Rpi master to read data multiple times from the same slave buffer before it is updated? In most code examples I see the comment "Read complete- expose buffer to master" when they perform this code:

/* Read complete: expose buffer to master */
if (0u != (I2CS_I2CSlaveStatus() & I2CS_I2C_SSTAT_RD_CMPLT))
{
/* Clear the slave read buffer and status */
I2CS_I2CSlaveClearReadBuf();
(void) I2CS_I2CSlaveClearReadStatus();
}

So I thought if I updated the slave buffer and then called this it should be fine.

Any advice is greatly appreciated.

Cheers,

mwors7

Hello,

I use a PSoC3 (CY8C3246PVI-147) on a PCB to drive brushed motor drivers. I'm experiencing some problems using the PSoC when it receives some external electrical discharges: the PSoC momentarily shuts down, blocking communication and also the movement of the motors.
Are there any measures that can be taken outside the PCB or through-hole components so that these discharges can be 'discharged' directly without shutting down the PSoC?
Thank you for your help.