PSoC™ 5, 3 & 1 Forum Discussions
Hi all
The is idea:
I got two MCU, Psoc (BLE), PSoc 5 and an external memory (SPI FLASH). The procedure would be:
1) PSoc 4 (BLE) receives an image (bootloadable#1) from external device and record this image in external memory.
2) After that, "bootloader 1" starts and the image is moved from external memory to internal memory of PSoc 4
3) PSoc 4 (BLE) receives another image (bootloadable#2) from external device and record this image in external memory (over the previous one)
4) I disable the UART/SPI block (to avoid noise in the tx/rx lines), and from PSoc5 "bootloader 2" starts and the image is moved from external memory to internal memory of PSoc 5
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
This is the idea and the steps 1) and 2) are working.
The step 3) is similar to step 1), with the difference of the bootloadable (one is for PSoc 4 and the other is for PSoc 5), but when I try to transfer this image from external device to the Flash memory, in this case doesn't work.
Any idea? I have been using the cypress example for SPI based external memory bootloader project.
I attach the two logs, first one with the result of steps 1) and 2) working properly. The second one with the error when I try to do the step 3)
Thanks.
Regards
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Show LessHello.
When using this same program with the ADC_SAR block it works perfectly.
When changing for the ADC_SAR_Seq block it throws me this error.
I already searched the forum and I can't find anything that can help me.
regards
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I want to use DMA to transfer data from the Status Register component to external memory at a speed of 5MHz.
(Use 5MHz for the Hardware Request signal (drq) of the DMA component.)
However, the access speed of the external memory becomes 2.5MHz. What is the cause.
[Clock settings]
IMO :Internal OSC (24MHz)
ILO :100kHz
PLL :Input=IMO, Nominal=60MHz
Master Clock : PLL_OUT(60MHz)
Bus Clock : 60MHz
Greetings
I wish to use this device in a new consumer product as it fits my goals in a single chip
- low pin count
- low cost
- small footprint
- capsense with slider
- USB
- I2C
- Wide Operating voltage from 1.7V
I am getting confusing feedback from Cypress agents on whether I should choose this device or a PSOC4 with 64QFN configuration as there is a push towards PSOC4 with CM0 core.
I want to know the official position regarding this device and what is the availability ahead.
Regards
Jerson
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I need a very simple PSOC program.
Note :- I know how to read a character but not sure how to read a string in PSOC.
Thanks,
Abinash
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