PSoC™ 5, 3 & 1 Forum Discussions

Hi community,

I want to configure the programmable micro USB port of my board (CY8CKIT-059 PSoC 5LP) as a CAN bus. Plan is to build up a modular CAN bus wherein I can quickly plugin new devices. For the wiring plan is to use the outer 2 USB wires (GND VDD) as power supply and the inner pins (micro USB's DM and DP) for CAN bus TX RX.

Therefore, I have to be able to define psoc's mircoUSB's DM and DP ports 15[7] 15[6]as In/Output for the CAN TX RX. However, DP and DM pots can only be defined as "Strong Drive" and "Open Drain, Drives Low". I could manage to work pins as a programmable digital output, but sadly I can't make them  to work as an Input.

Therefore, I want to ask for help on how define mircoUSB's DM and DP as readable Inputs and if not possible I want to know why.

Since the example code for programming micro USB as USBFS UART https://www.cypress.com/documentation/code-examples/ce95396-usb-uart-psoc-35lp works as a serial two-way I-O communication, I'm quite confident that DP and DM should be definable as inputs as well.

Thanks for helping!

Best Regards Robert.

Hi ,

I am completing my project. I have a plan to make a prototype board. The program is tested on development board CY8CKIT-030. the PSoC part number is CY8C3866AXI0-040 on the board. What is the minimum circuit requirement to make a prototype board and program the prototype board using Miniprog-3. Can someone share the schematic.

Thank you

AK Singh

Hi

I am using creator version 3.3 and pSoC 5

In my project I have a folder with two files C and H and they have some functionality we need for many project.

So far we were coping those file to each project separately. (the files are compile OK in the project)

We decided to create a code library that can be linked and share among the project

I have created a Code library project with this two files and gave it a name.

Let say that the library name creates is "MyLib.a" and the H file is "MyFile.h" and also I Have "MyFile.c".

The library project compile OK and created the Library "MyLib.a" .

Now I went to any project I have that uses those files embeded in my code and removed the code from it. Assuming now i can add the library and the include the h file and all will be fine.

First I added the Library in the linked in the library path and library name using the browse option we have in the IDE

The H file have been assign in the project include folder and added to the project

When I complied it the it complain that he cannot fie the file "MyLib.a" where for sure it exist and i have set the right path for it

I also try to add it as dependencies and any information I found in.

I am familiar with adding library in different type of high language and here I failed.

I tried to search the forum before putting my case here and didn't find any found some and followed them instruction but one works.

I tried also to copy this library file "MyLib.a" to my project folder but it didn't worked.

Please help is required on that issue and i am sure that someone came across it and have a solution

Regards and Thx

Arie

Dear Community,

I am fairly new to psoc5lp and have a "CY8CKIT-059 PSoC® 5LP Prototyping Kit" , trying to achieve the following task with it:

# sample both SAR ADCs simultaniously with sample rate of 768kHz (using external CLK of 24.576MHz)

# transfer ADC-conversion results via SPDIF transceiver component at sample rates of 48kHz or 96kHz (maybe 192kHz, if possible)

What I do know:

# SAR ADC has some limitations, depending on bit-depth, external/internal reference voltage. Lets settle for 10 bit and external reference (proper decoupling assumed).

# It is possible to transfer conversion results directly to SPDIF component via DMA, which saves a lot of MCU ressources

# It might also be possible to use a Digital Filter Block as well, i.e.: ADC -> DMA -> DFB -> DMA -> SPDIF . That would be benifitial for noise reduction/low pass filtering

# DFB can be programmed via assembler instructions

What I do not know and want to figure out with your help:

# depending on the output sample rate the ADC results have to be downsampled by a factor of 4, 8 or 16. In order to get the best possible SNR I would like to implement avereraging in combination with downsampling (otherwise I could set the ADC to exact same sample rate as the SPDIF ouput stream)

# I guess, it should be possible with a custom DSP-program, but I have absolutely zero assembler-skills

# I can imagine that a simple moving averaging algorithm could be implemented in software, using a end-of-conversion interrupt. BUT: (a) that would cause a lot of CPU load at 768kHz and (b) I am not sure how to attach this software data-handling process to the DMA

Since the MCU does not have anything else to do, a pure software solution (means: without DMA) is probably feasable, but I have concerns about the high CPU load.

Do you have any ideas concerning downsampling/averaging and DMA? How would you approach this?

regards!

Dear support,

for a new project, I'm evaluating to import a VHDL component into PSoC 5LP.

Since I'm not expert with both VHDL and Verilog, I'm wondering if there any VHDL to Verilog translator for PSoC 5.

Thank you

Is there an industrial version of miniprog 3? I have had some problems with device programming, I get a programming error and I have already replaced the device 4 times, I don't know the reason for the failure.

Hello there,

I am trying to design my own PSoC5lp board, and are having some confusions amont some points.

1. According to the "PSoC® 3 and PSoC 5LP External Oscillator - AN54439", I am able to attach an external oscillator (like TXCO) to the XtalIn so that the clock would route from MHzECO to the clock tree. If I power the PSoC5lp using 5V at Vdda and Vddd, could I use an 3.3V output TXCO? Or more of how many volt in terms of "high level" does XtalIn require to operate correctly?

2. From TRM, I see there exist an 1.2V voltage reference for DelSig. Is there a way to access it?

3. If I power the PSoC5lp's Vdda at 5V, but for a specific Vddiox I do 3.3v, and if I use a pin under this 3.3V Vddiox section as analog input/output, could the voltage at this pin higher than 3.3v? Let say can I output 4V from a DAC out from a pin under a 3.3V Vddiox?

4.  "PSoC 3 and PSoC 5LP Hardware Design Considerations" suggests 0.1u and 1u capacitors for decoupling purposes, but from power supply impedance perspective (PDN analysis), we know that combination of those two values normally would not give us a good low impedance power supply input impedance across all frequencies. Is that ok if I do capacitors from 10n 100n 1u 20u in parallel for all of those supplies pins for a very strict EMC design? Does Cypress suggest 0.1u and 1u due to internal LDO's stability constrains?

If anyone can help me out from those questions I would really appreciated.

Thanks a lot!

Hanpeng