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Hi all,
I've found a few threads on this but none of the ones I've seen lead me in any direction.
Is it possible to access sram directly from a verilog component? if not is it possible to do it with the DMA? If so could someone please provide some instructions so I can start looking into it?
I'm interested in doing some calculations with the cpu and then taking that array and passing it to the verilog component.
I know this can probably be done with an api, but is that the only way? I imagine this would be slow since it would be transferring the data rather than sharing its address, and I would be passing a large amount of data so I'm trying to make it with as little cpu overhead as possible.
Thanks,
scarlson
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PSoC 5LP
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Short answer: No, you cannot access memory from a UDB-based verilog component directly. A way out could be to use DMA which reads from the fifo.
Bob
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scarlson,
Additionally, to pass data to Verilog component you can use Control Register (like in this example), or you can instantiate control register inside Verilog code directly (same result).
PSoC5 has limited capacity for Verilog code. Probably one unsigned 8-bit multiplication, or about a dozen 8-bit additions may eat many PLD cells and most P-terms. As P-terms reaches 90%, the Max frequency will drop down to ~30MHz due to latency. Is there something specific calculation you want to off-load to Verilog (like Log function)?
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Here is codic implmentation for transcendental functions that may be of
interest -
http://www.cypress.com/forum/psoc-community-components/cordic-v20
Regards, Dana.
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it sounds like the DMA reading the fifo *might* be an option, as long as the psoc 5lp can has enough cells.
well I was interested in creating a simple accumulator and averager that's always running using the dma but from the sound of your post i don't know if that's an option anymore?
I was also interested in taking the log of a value in an array and returning it to its same place all without passing the value to or receiving it directly with the cpu..
and thanks danaaknight, I will look into that code when I get home tonight.
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it sounds like the DMA reading the fifo *might* be an option, as long as the psoc 5lp can has enough cells.
well I was interested in creating a simple accumulator and averager that's always running using the dma but from the sound of your post i don't know if that's an option anymore?
I was also interested in taking the log of a value in an array and returning it to its same place all without passing the value to or receiving it directly with the cpu..
and thanks danaaknight, I will look into that code when I get home tonight.
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scarlson,
for continuous averaging use DFB component, for MAC use this one
Yo can pass it an array of 1024 numbers (max). It is not moving average though.
For single-cycle (low accuracy) Log function implementation in Verilog you may check:
http://www.edn.com/design/systems-design/4424046/Single-cycle-logarithms---antilogs.
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Wow, thats quite an introduction for the DFB component on that page. I'm really glad I asked this question I don't think I would have found it on my own.
I'll check it out tomorrow afternoon and let you know how it goes.
As for the log function, it may work, I will have to test it out to see, I can give up some accuracy, as long as it's relative.
Thanks a bunch guys