According to the PSoC 5 datasheets:
"VDDA must be the highest voltage present on the device. All other supply pins must be less than or equal to VDDA."
What happens if, briefly this is not true? What if the VDDA supply cuts out for a moment? Can this cause actual damage to the chip?
What if it happens several times, or for a prolonged period of time? Can this cause damage to the chip?
How exact does this need to be? What if VDDA = 4.95v and VDDD = 5.00v?
We don't recommend to do that. As per Cypress VDDA must be greater than VDDD. If this condition not follows then there might be a back current produced. We asked our internal team for more clarification for the same.
Please refer to this KBA GPIO (Vddio) operating at voltage higher than Vddd and Vdda in PSoC3/5
Thanks for the reply, but it doesn't really answer my question: What is the tolerance on this condition? And what happens if the condition is violated by accident?
Imagine that I use two separate 5v regulators, one for VDDD, and one for VDDA (this helps to keep the digital noise off the VDDA line).
These two regulators will have some tolerance, so one of them might be producing 5.02v, and one might be producing 4.98v.
I have separate VDDD and VDDA regulators, both nominally 5v. A glitch happens on the VDDA line, bringing it down to 4.5v for 1ms.
I have separate VDDD and VDDA regulators. The VDDA regulator has more capacitance and so takes longer to ramp up to 5v than the VDDD regulator.
These three are all realistic cases. What happens in these cases? Are these OK? Will they cause damage to the chip?
We do not have data for the precise scenarios mentioned by you. However, there were test cases when VDDD ramp up was greater than VDDA. In such cases it was observed that there were glitches in the GPIO behaviour, also the device worked with unexpected behaviour with GPIO. So, it would be better if VDDA is greater than or equal to VDDD as per architecture. Until you do not exceed the absolute maximum limitations, your device will be safe.