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Hi,
I'm trying to build my project, but I get the following error which I can't seem to solve:
sta.M0019: hold time violation found in a path from clock (cyBUS_clk) to clock (Pin_5(0)_ SYNC/OUT)
My project includes 1 SPI master and another (not related) SPI slave blocks.
I suspect the problem is due to the SPI slave which is controlled by an outside clock.
I've attached my project top design schematics.
Thanks in advance,
Igal Nudelman
Solved! Go to Solution.
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PSoC 5LP
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Welcome in the forum, Igal.
Your SPIS component's MOSI-pin (Pin_4) uses double sync at its input that is causing the warning. When set to none (no syncing) the warning passes.
Additionally: I would suggest to use an internal clock, since there is no need in your case for an external one on Pin_33. This clock is not controlling the bit-rate, it is for the component's internal updating of the states.
Bob