I don't know where to post this, so move it if necessary. I finally removed all of the proprietary part of the project, and can post it.
I have a project for a 5LP-039, a 67 mhz part, and if I use almost any clock, starting with a 66mhz clock, it gives 2 errors, that you cannot get rid of by using Sync Components (which always worked in the past) or even reducing the bus speed to 33 mhz or somewhat below. However, if you remove the DMA component, the errors go away at 66mhz! PSOC Creator 4.4
This is not posted to get I*n to work on it. They stated they will not fix any problems with PSoC creator. However, I am giving this to the wider audience of engineers so they can be aware of the issue and avoid it if possible.
The errors are (with the path name garbled on purpose) are following:
Warning: sta.M0019: PSOC_Creator_timing.html: Warning-1366: Setup time violation found in a path from clock ( CyBUS_CLK ) to clock ( CyBUS_CLK ). (File=Z:\S\_old\SurfacePanelMCU-5V0B-SPDL_OLD copy\PSOC_Creator.cydsn\PSOC_Creator_timing.html)
Warning: sta.M0019: PSOC_Creator_timing.html: Warning-1366: Setup time violation found in a path from clock ( Clock_BaudRate ) to clock ( CyBUS_CLK ). (File=Z:\S\_old\SurfacePanelMCU-5V0B-SPDL_OLD copy\PSOC_Creator.cydsn\PSOC_Creator_timing.html)
I also found that if I reduced the speed of absolutely everything to 24 mhz I could usually (not always) stamp out the CyBUS_CLK error. At that point, the sync component can fix the timing issue on the external clock.
I suspect, if I*n uses the same compiler technology for PSOC4 and PSOC6, those units may have similar issues, except for the fact that those are usually UDB crippled, with extremely few UDB's and/or extremely limited routing options, so there are fewer routing calculations that must be done. That typically means these issues won't occur.
I tried using a PSOC4 during the time I*n refused to be a manufacturer of PSOC5's, and it did not work well due to limited route-ability and limited UDB's. During that time, I*n nearly put us out of business, and I suspect that prospect makes everyone at that company very happy not to have to deal with the engineering trash we represent. I will always distrust I*n from now on. Fool me once, shame on you. Fool me twice, shame on me.
I now look for components from other manufacturers first.
Solved! Go to Solution.
Thank you very much for your interesting informaiton!
BTW, the title may be wrong, it should have been "PSoC 5LP, Clock Configuration issue", right?
In the Static Timing Analysis report, it reads
Maximum Frequency of CyBUS_CLK: 32.937 MHz
In my experience except 8bit or lower MCU, Bus clocks are safe to be slower than 1/2 of the core clock.
So this might be reasonable as the architecture, but may not be reasonable for the real use.
Anyway, I also tried to find what can be done, so far, the following configuration seems to work
So with the current device and the current tool, it seems that we can survive up to 49MHz.
And if you need faster performance, looking into other faster devices seems to be the correct approach.
P.S. Yes, I'm really feeling sad that Cypress/Infineon stoped enhancing PSoC Creator and/or devices with UDBs.
I love 5LP and still wishing to see enhanced 5LP and/or updated PSoC Creator in the future 😉