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PSoC™ 5, 3 & 1 Forum Discussions

MaMi_1205306
Level 7
Level 7
500 replies posted 50 solutions authored 25 likes received

Hi,

I would like to confimrm about UART component of PSoC5LP.

After clearing the reset by setting the XRES pin to 'H',

About 5ms later,

'L' for 1us is output from the TX of UART.

This instantaneous 'L' period is a problem.

Do you know the reason why this problem occurs?
Also, do you know how to solve this problem?

Regards,

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1 Solution
Vasanth
Moderator
Moderator
Moderator
250 sign-ins 500 solutions authored First question asked

Hi,

The default state of the General Purpose IO pins in PSoC 3/5 is High-Z.  But this can be changed to either Pull Up or Pull Down, by modifying the "Power On Reset" parameter in the "Reset" tab in the GPIO configuration.

When the default state is changed in the cofiguration, this information is stored in the Non Volatile Latch (NVL) and the pin will be configured to the desired state during POR.  However, the NVL has very limited write cycles (1K at 25C and 100 at 0 to 70C).  Hence do not change the default state of a pin during the design stage to avoid failure of the NVL and the pin (see warning in the above screen shot).

Best Regards,

VRS

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Vasanth
Moderator
Moderator
Moderator
250 sign-ins 500 solutions authored First question asked

Hi,

The default state of the General Purpose IO pins in PSoC 3/5 is High-Z.  But this can be changed to either Pull Up or Pull Down, by modifying the "Power On Reset" parameter in the "Reset" tab in the GPIO configuration.

When the default state is changed in the cofiguration, this information is stored in the Non Volatile Latch (NVL) and the pin will be configured to the desired state during POR.  However, the NVL has very limited write cycles (1K at 25C and 100 at 0 to 70C).  Hence do not change the default state of a pin during the design stage to avoid failure of the NVL and the pin (see warning in the above screen shot).

Best Regards,

VRS

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