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Antonio
Level 2
Level 2
First like received 10 replies posted 5 replies posted

Hi everyone,
in one of my projects I communicate via a two-wire 485 serial port with a PC, the baud rate is 115200 bps, but out of necessity I have to increase the speed and therefore I set the baud rate to 460800 bps but it no longer works, I also tried using the external XTAL as a source, does anyone know if there are any limitations or special precautions?

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RaAl_264636
Level 6
Level 6
50 sign-ins 25 sign-ins 10 solutions authored

Hi Antonio,

it should work if you set PLL output to 48MHz or 60MHz. In fact, the PLL incorporates a divider and a multiplier.
I mostly use multiples of 6 or 8 MHz as PLL frequency for my designs because internal 24MHz IMO divided by three or four gives those "base" frequencies. That's the reason why my screenshot showed 72MHz.

However, the restriction of 67MHz max for a 5LP device is strange. I think you're using the old PSoC 5 device family (non LP), right?

14.7456MHz is another crystal frequency suitable for accurate UART baudrates as well as 11.0592. Glad that it works now. You can still try if it would work with internal clock.

Regards

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RaAl_264636
Level 6
Level 6
50 sign-ins 25 sign-ins 10 solutions authored

Hi Antonio,

please describe your current hardware. Are you using a CY8CKIT-059 with PSoC5LP UART connected to the onboard KitProg? If yes, the official maximum baudrate supported by KitProg is 115200Bd - please read this topic for getting more speed with it. If you're on a custom hardware, please describe it or show schematic circuit.

Regards

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Antonio
Level 2
Level 2
First like received 10 replies posted 5 replies posted

Thank you for the reply, I'm using a custom hardware, that I use since 15 years, PSoC 5 LP (CY8C5868AXI-LP032) is connected witha differential bus transceiver SN75176B, with RO pin and DI pin connected directly at PSoC, and RE and DE connected togheter on another PSoC pin. I use the UART component ver 2.50, in Full UART mode, 8 data bits, no parity, 1 stop bit and no flow control, I always used this configuration without problems at 115200, but as soon as I turn into 460800 it stop working...is there a limit?

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RaAl_264636
Level 6
Level 6
50 sign-ins 25 sign-ins 10 solutions authored

Hi Antonio,

hardware limits would be the used RS485 transceiver and the clock supplying the PSoC UART. The UART uses either 8x or 16x oversampling, so you'd need 3.6864MHz or 7.3728MHz with a clock accuracy of 2% or better. PSoC Creator should throw a warning when building the project regarding clock issues. I'm using the UART at 2Mbps and didn't notice any issues.

If your hardware runs with 115200bd, but not with 460800bd it's either because the clock is not accurate enough or maybe a software buffer is too small (now, because you're four times faster).

For debugging the issue, I'd recommend to disconnect the RS485 bus, make a small test project where the RS485 bus continously transmits 0x55 - this should give a symmetrical waveform which can easily be checked with an oscilloscope. For both speeds, you should see the waveform and you can verify if the accuracy is good enough.

Regards

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Antonio
Level 2
Level 2
First like received 10 replies posted 5 replies posted

Thank you for the reply,

I'm using an external 24 MHz xtal as the source, I was hoping it would be accurate enough, but I could be wrong. I have already connected an oscilloscope to the receive and transmit pins and implemented a simple echo project, if I send a hex less than 20x0 it returns the correct value, for all higher values it sends 40x0 more, so instead of 20 it sends 60, it seems from the graph that it is unable to send all 8 bits but stops at the seventh

 

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RaAl_264636
Level 6
Level 6
50 sign-ins 25 sign-ins 10 solutions authored

Hi Antonio,

that sounds strange. Can you provide your PSoC Creator project?

Regards

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Antonio
Level 2
Level 2
First like received 10 replies posted 5 replies posted

in the image below there is the blu wave is the character I sent from PC and the PSoC receive, the red one is the character PSoC sent and I received on the PC

screenshot.png

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RaAl_264636
Level 6
Level 6
50 sign-ins 25 sign-ins 10 solutions authored

Hi Antonio,

that means the PSoC transmits what it receives, doing a simple echo? If yes, can you also check the DE/RE signal? Have you verified that the PSoC has received the 0x55 char by debug session? This could help identifying if the receiving or the transmitting part is the issue.

- Is the UART doing the RE/DE handling itself (HW-TX Enable set in configuration) or is it controlled by software through GPIO?
- Are you using the standard API?

Regards

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Antonio
Level 2
Level 2
First like received 10 replies posted 5 replies posted

PSoC receive the correct character 0x55 (I saw it in the debug mode, and I saw it in the blu wave) So I think the issue is on the transmitting part.

- I set the HW-TX Enable, join the DE/RE signal in a PSoC pin.

- I use the standard API

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Antonio
Level 2
Level 2
First like received 10 replies posted 5 replies posted

I saw the DE/RE signal, it seem works good, is high only when the PSoC transmitt 

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RaAl_264636
Level 6
Level 6
50 sign-ins 25 sign-ins 10 solutions authored

Hi Antonio,

okay, then let's dig deeper into it. First, from your screenshot, it looks like the transmit bit timing is somehow disturbed.

RaAl_264636_1-1704996967830.png

The yellow line is one bit slot of the receive signal. The blue lines equal the length of the first slot (start bit) of the transmit signal and are copied to each bit slot. The green line is from the receive signal and shows the duration from the first falling edge to the last rising edge. As can be seen seven bits are okay, but the eighth bit seems to be swallowed. You can also see a deviation from Rx (yellow line) to Tx (red waveform).
I also did the opposite from Tx to Rx:

RaAl_264636_2-1704997589518.png

At the middle of the sixth Rx databit an edge can be seen, which is a huge deviation. I'd say you definitively have a clocking issue.

Please show the clock tab of the DWR (Design Wide Ressources) sheet of the project. Here's mine along with the internal clock settings for a UART setting of 2MBit.

RaAl_264636_3-1704997941694.png

Local Clock_1 is derived from main clock and used as external clock to the UART, using oversampling rate of 8. For the IMO, I'm using the 24MHz setting with USB enabled which results in +-0.25% accuracy for the IMO (if USB is not used it will be 4%).

I also did a small test: I set the IMO to be 24MHz with USB disabled (4%) and the CPU clock to be also 24MHz. The UART is using internal clock and I got a warning about clock accuracy out of range for 115200bd and 460800bd. What is your CPU clock value? Are you using the PLL to get higher CPU clock?

Regards

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Thank you for the reply,

I use an external 24 MHz crystal from which all the others are derivedscreenshot2.png

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Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

@Antonio ,

Four things to consider:

  1. Some RS485 transceivers have a upper data rate limit because designed-in slew rate limitations.
  2. Consider the length of your RS485 cable.   Longer means lower data rates because of lumped sum capacitance and serial wire resistance.
  3. To accurately support 460800 bps the UART uses an 8x input clock.  Therefore the input clock needs to be 3.6864 MHz.  Possible but it probably needs a crystal to achieve a maximum tolerance level.  See next point.
  4. The general rule-of-thumb is that the baud rate tolerance allowed is < +/- 4%.  Any more than that may accumulate a bit timing error across the byte being decoded at the other end.  Therefore, to achieve 460800 bps, the 8x input can be between 3.538944 MHz to 3.833856 MHz.   I sincerely doubt if you can achieve this level of accuracy from the IMO even with the PLL unless you use the IMO in USB support mode.   Attached is a simple example project (no code just TopDesign and Clock setup) as a starting point.

 

Len
"Engineering is an Art. The Art of Compromise."
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Thank you for reply,

1 and 2- I checked the datasheet of the transceiver and there is nothing written about the limit at 460800 bps, however I use an oscilloscope between the PSoC and the tranceiver, precisely to exclude problems with the length of the cables (which in any case is less than metro), and to investigate the fact that there appears to be a problem at the output from the PSoC rather than at the input from the tranceiver.

3 and 4 - I'm using an external quartz just to be sure of the reliability of the clock, it's 24 MHz, maybe I need to investigate this, I set the dividers to get 3.686400 MHz, maybe the accuracy is not enough?

 

 

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RaAl_264636
Level 6
Level 6
50 sign-ins 25 sign-ins 10 solutions authored

Hi Antonio,

that's why I asked you to show the clock tab settings of your project... 😉 I'm pretty sure you won't need an external crystal, but the clock settings need to be properly.

Regards

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Now that you've seen the clocks tab, do you have any suggestions? I'm stuck and I don't know what to do

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Hi Antonio,

I can't see anything regarding clock tab. Did you attach a screenshot? EDIT: sorry, I missed the screenshot above. I calculated your deviation, you're around 7%, definitively too much. I suggest to use the PLL in combination with USB clock enabled, even if you don't use USB (currently).

I wonder why your screenshot shows 0% accuracy. Anyway, if you don't want to use the PLL and keep the XTAL you should use a crystal with a frequency suited for UART baudrates, e.g. 22.1184MHz.

Regards

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screenshot2.pngscreenshot3.png

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Hi Antonio,

thank you for the screenshots - please see my last response where I edited my text.

Regards

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I'm not clear on how to use the PLL in combination with USB, should I still use the 24 MHz PLL as the UART clock source? or should I use USB clock?

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RaAl_264636
Level 6
Level 6
50 sign-ins 25 sign-ins 10 solutions authored

Hi Antonio,

try the settings below. Note that the 0.25% accuracy for the 24MHz will only be shown after enabling USB clock.

RaAl_264636_0-1705052379512.png

After doing this and rebuilding the project, from the clocks tab divide the desired frequency by the nominal frequency. If the result is between 0.98-1.02 your UART should work properly.

A question about your current clock setup: what is the reason why you reduced the CPU clock to 8MHz? Is this an energy constrained device?

Regards

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I tried this solution but PSoC Creator doesn't allow me to confirm, maybe my device doesn't match this solution(see attach). Anyway, in another board I found a xtal at 14,7456 MHz and I substituited it with mine and work well

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RaAl_264636
Level 6
Level 6
50 sign-ins 25 sign-ins 10 solutions authored

Hi Antonio,

it should work if you set PLL output to 48MHz or 60MHz. In fact, the PLL incorporates a divider and a multiplier.
I mostly use multiples of 6 or 8 MHz as PLL frequency for my designs because internal 24MHz IMO divided by three or four gives those "base" frequencies. That's the reason why my screenshot showed 72MHz.

However, the restriction of 67MHz max for a 5LP device is strange. I think you're using the old PSoC 5 device family (non LP), right?

14.7456MHz is another crystal frequency suitable for accurate UART baudrates as well as 11.0592. Glad that it works now. You can still try if it would work with internal clock.

Regards

Thank you very much, using your settings and works very well, so I now have many solution, one hardware using a xtal with a right frequency, and a software solution using clocks properly.

I don't know how to thank you, you were very kind, thank you very much.

Best regards

 

ps. anyway I'm using a PSoC 5 LP

RaAl_264636
Level 6
Level 6
50 sign-ins 25 sign-ins 10 solutions authored

Hi Antonio,

indeed there are many solutions possible, especially with PSoC 😄 Using an external crystal depends on the accuracy requirements of the project. If you want to create "any" clock you can search the forum for DDS24/DDS32 component. And I'm pretty sure there are other solutions possible. Currently I'm thinking of creating a component for fractional clock dividing.

Regarding the PSoC 5 LP device, you wrote that you're using CY8C5868AXI-LP032 which is indeed a LP device, but it's restricted to 67MHz. I always thought the LP devices have 80MHz and the non-LP devices have 67MHz, so it was my fault. Sorry for that.

Regards

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