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PSoC™ 5, 3 & 1

rmlowe01
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Hi, I am wondering how to transition a design from the PSoC 5LP to the PSoC 3 with the minimal amount of changes possible (not having to redesign the hardware and software). I am wondering if there are any notable changes I must be aware of besides the specs difference. Of course, a simple change of device and copy and paste will not build or compile successfully. Any helpful information will suffice. The reason I am downgrading to an older chip is because there is a massive chip shortage with a year lead time on a 5LP chip that is currently being used in the design.

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Len_CONSULTRON
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rmlowe01,

The PSoC3 generally has the same resources as the PSoC5LP.  This means that if you pick a PSoC3 that has the same number of resources as the PSoC5LP in your design, the Application Build phase shouldn't complain.

I can't vouch that you will find an equivalent pinout.  If no equivalent, you would have to change the layout.

Another potential issue:  The PSoC5 uses the ARM (a RISC micro) and is generally quicker at executing code than the 8051.  There might be a performance issue depending how you are taxing the CPU.

Another issue is that the Keil compiler used on the PSoC3 has some slightly difference syntax.  Therefore porting the PSoC5 code from your design to the PSoC3 may require some adjustments.

Here my suggestions:

  • Find a PSoC3 with the closest match to the PSoC5LP in your design.
  • Contact a Infineon sales rep to see if this PSoC3 is available in he timeframe you need.
  • Make a copy of the PSoC5 design project and select the chosen PSoC3 device for this project.   Try to compile your PSoC3 project and see what warnings or errors pop up.
Len
"Engineering is an Art. The Art of Compromise."
rmlowe01
Level 1
First reply posted First question asked Welcome!
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Len_CONSULTRON,

Thank you for this.

Another thing that came to mind was the amount of SRAM that the PSoC 3 (8K) has compared with the 5LP (288K). In the 5LP design, according to the resource monitor, we are using about 18% of the SRAM resources. Not sure if that should be a concern moving forward. If your application builds properly, is it safe to assume that the PSoC 3 resources are enough? Obviously, I should still test it in the field to see if there are any performance discrepancies. All other spec considerations appear to be enough (Available function blocks like UDBs, operating frequency, etc).

We have found a PSoC3 with similar pinout definitions and same number of pins (1 to 1 correspondence).

Transition: CY8C588LTI-LP097 -> CY8C3865LTI-014 (Please feel free to comment if I may have missed anything in terms of packaging difference, or anything else that may warrant a change in PCB layout.)

Yes, the change in syntax regarding software compilation makes sense given the fact that the two chip families use different compilers.

So there will be two main obstacles to overcome which would be building the hardware logic (application build phase) and compiling the code. 

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EvPa_264126
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another problem PSoC 5 Endian vs PSoC 3

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pacr_284376
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I did it the other way round a couple of years ago. Biggest issue was Endianess (as also stated by EvPa_264126). Depending on your libraries this could be a problem somewhere in the code.

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