I'm having a timing violation caused by the setup pictured below. I need my bus clock set fast, but for some reason this setup with the shift register is putting a limit of ~20MHz on it... Any idea why or how to remove this limit? I already tried just slowing the bus clock down, but that breaks the project in other ways.
I t*seems* to work fine but we're about to move into production so I need to be certain this isn't a problem waiting to manifest.
A reduced version of the project showing the problem is attached. Thanks in advance.
Dan
Dan,
The issue you're seeing is that the GPIO pins cannot operate at full CPU clock speeds. (See GPIO AC spec below)
This is why the max in the "Timing Violation" section is 22.188 MHz (you must have set the VDD in your design to below 2.7V.)
There are two ways to address this.
- In TopDesign, get rid of the ADD gate from SDA_0 and route control_1 directly to the shift_in input. This keeps it all internal where the clocking frequency is much higher.
- Make sure that you never switch control_1 or CTRL any faster than 22 MHz. Then you can ignore this warning and all is well. Given that you are probably changing control_1 in code, you probably can never achieve a switching time faster than 22 MHz. That's probably why it's working and you have no issue.
Dan,
The issue you're seeing is that the GPIO pins cannot operate at full CPU clock speeds. (See GPIO AC spec below)
This is why the max in the "Timing Violation" section is 22.188 MHz (you must have set the VDD in your design to below 2.7V.)
There are two ways to address this.
- In TopDesign, get rid of the ADD gate from SDA_0 and route control_1 directly to the shift_in input. This keeps it all internal where the clocking frequency is much higher.
- Make sure that you never switch control_1 or CTRL any faster than 22 MHz. Then you can ignore this warning and all is well. Given that you are probably changing control_1 in code, you probably can never achieve a switching time faster than 22 MHz. That's probably why it's working and you have no issue.
DaGr,
Adding double-sync option to the Pins input boosts max clock frequency to 62 MHz (BUS_CLK = 24MHz) or 81MHz (at BUS_CLK=48 MHz). Simply put, the ShifReg input should be synched with the BUS_CLK. Using Sync component boosts max clock to 105 MHz (irrespective to BUS_CLK).
The schematic can be further simplified using custom small Sync32 component
Sync32 custom component for PSoC5 and PSoC4
/odissey1
Option 1. Configure Pins input to dbl-sync.
Option 2. Use Sync component to sync Shift_in signal to the clock
