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we have a timing sensitive design (part of it), that is hand optimized for max performance (highest possible clock) to meet the setup and hold timings. Most other parts do have much lower requirements. It seems that cydsfit will optimize all parts with the same rules.


Is there a way to define a timing constraint for some signals or clock domains, that will become a much higher priority while routing over others?


We also designed the project with Creator 3.0. After updating to 3.3 the timing results a much lower. Therefore we had to switch back, because the design is tested and in production.


Kindly regards,



1 Reply
Level 9
Level 9
100 sign-ins 5 likes given 1000 replies posted

You might consider filing a CASE and provide both Creator versions, asking


the question why timing changed substantially.




To create a technical or issue case at Cypress -






“Design Support”


“Create a Support Case”




You have to be registered on Cypress web site first.




Warp Verilog has very course timing controls, very limited.




Regards, Dana.