Things are not solved until they are solved. 3 phase 5 KHz tunnable signal. how to tune it?

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luisji
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The original Re: 3 identical shifted signals, 5 Khz, tunnable by program, with sensors 

I had to make the new question because the previous somebody marked it 'as solved', then, when I could return to this problem and asked the next subquestion, nobody see it because 'it is marked as solved', although it is far away of being really solved.  I'd ask, Solved for who?  If the person with the question can't handle the answer as something that solves the real problem, it is not solved. 

So, excuse me for the delay.  I'm now back with this problem.    I hope CONSULTRON could continue helping me as he gave me the example I'm working with.

As I stated first, I need to move frequency about +- 12% from a frequency, that is a little lower than 5 KHz, in order to sustain some resonance on the system.  i have seen what you sent, I understand that the clock was defined as the 8 bit period (256) multiplied by 5,000 Hertz, so you get a clock of 1.28 MHz. but as I need to move smoothly the frequency from the program (see the image freq_resonance attached), I see at first sight two posibilities: 

1. To change the frequency on the clock with  Clock_SetDividerValue(uint16 clkDivider) or

2. To change Period of the first PWM 

The problem is that I don't know which values are elegible in case 1. and that the steps that would be available in case 2. are very wide (18.35 Hertz per step), and, if the range is about 564 Hertz for each side, with 30 steps I'll never can sustain resonance (I would correct from a derivative control factor, but if it doesn't work, it would become a PID algorithm). I think that the minimal step should be about 4 or 3 Hz.  At the beginning, the program will scan the range until it finds the resonance frequency.  The input for the program will be a sound, so when amplitude reach a peak, the program has to avoid loosing resonance moving frequency as needed.  The resonance freq. could vary a little with rise of temp, the system has to make the changes needed, if amplitude begin to decrease, it has to oscilate slowly to verify on which direction it reaches the peak again (zero slope).  I think that the green range, of about 500 Hz will be enough, but I'll know it until the experiment be phisically implemented.  

 Another thing that I want you to help me is the next:  I have to sustanin resonance, but I want to read and display several sensors (a microphone, temp, presure, amp, volt, etc).    How can I do all that?   That is, I think I have to avoid to wait for response, it be a sensor, the display or whatever, so I think I would have to have a clock and each component would check if the delay time is reached for it, each round of the program, so for instance, it could send another data to display or it could read an ADC register if a flag is now on on each one. This way I don't interrupt the frequency generator. (supposing that it become stopped while a delay instruction is working)  So, if You could help me to make clear this item I'd thank  you a lot.

I have not reviewed the other example you gently sent me, but from a surface sight, I think that LUT  can't comply with the requirement of min step here stated, but you can correct me if I'm wrong.   

I wonder if, as it is marked as solved (I don't understand what for is that costume of setting as solved this), this question will be seen and attended.   I hope it be...

Thank you again

Luis

I have checked the signal of the example in my psoc 5 and an image of it is attached as Fase1 y 2.  That means that I have saved some obstacles until having it working.  This is not much, but it is some advance.  I'm going to put more time on this project in next weeks.

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I have another question:  The clock goes at 30 KHz, the LUT has 8 positions.  I suppose that the signal can have six positions, as seen on the image in the red frame, because repeating these positions, the 3-phase signal can be reproduced. Although I see that the binary LUT input from 3 to 4 gives us less or more out states (isn't a way to have just 6 positions?)  Then, the 30 KHz clock, if divided by 6, gives us 5 KHz, but the LUT is 8 positions, and it is another sequence.  Then I don't know what will happen when state be 0 or 7, and how they affect clock and frequency

First you will notice the the required 3 phase outputs feedback to the same number of inputs.

Len_CONSULTRON_1-1633696207994.png

Because there are 3 inputs, the LUT MUST HAVE 2^3 = 8 states.  It cannot have only 6 states.  However it can have 6 ACTIVE states.  The other states are initial or illegal states which must be declared and resolved at the next clock cycle.

For example state 0 is an initial state.   When the 3-phase generator is running only 1 or 2 outputs can be on at a time.  Never 0 or 3 outputs.  The exception is before the clock starts the outputs are all 0s.  This must be resolved to one of the states  on the first clock cycle.

state 7 is illegal and should never be present.  However if for some reason it did, it must be resolved to one of the legal states.

Len_CONSULTRON_0-1633696188119.png


Next question is  how can I move frequency of the system from an API?   I see that there is a function:

Clock_SetFractionalDividerRegister()

or 

Clock_SetDivider(uint16 clkDivider)

that could be the one, but Can you give an example about how could it be in a program?  

Please see the excel doc attached.  I don't understand how to get the change on frequency with a clock who has a divider range stated in integers from 0 to 65,535, when I would need numbers between 0.88 and 1.12 with variations of 0.0004% in order to get 2 Hz steps.  

 

 First:  Clock_SetFractionalDividerRegister()  does not exist for the clock component selected to drive clk_3ph.  Only Clock_SetDividerRegister() which uses only integers.

If you want EXACTLY 2 Hz variance, you're out of luck.  

My project gives you +/- 1.92233756... Hz resolution.    It is 'better' than the 3 to 4 Hz resolution you asked for but not an integer.

 Changing the PLL output frequency from 78 MHz to 75 MHz will allow a 1 count divider change to clk_3ph to be +/- 2.0008 Hz.


Then, it surge another question:  If each time this API is used, the clock resets, if the system was in resonance, it would be lost if the clock restart out of the previous pattern.  Is there a way of preserving the pace, the rithm after the frequency has changed a litlle?


I understand that you don't want "glitches" in the sound when changing the frequency to find resonance.  The Clock_SetDividerRegister() function has two parameters.

 

* Parameters:
*  clkDivider:  Divider register value (0-65,535). This value is NOT the
*    divider; the clock hardware divides by clkDivider plus one. For example,
*    to divide the clock by 2, this parameter should be set to 1.
*  restart:  If nonzero, restarts the clock divider: the current clock cycle
*   will be truncated and the new divide value will take effect immediately. If
*   zero, the new divide value will take effect at the end of the current clock
*   cycle.

 

 Note the second parameter 'restart'.  If this parameter is 0 then the new clock divider will start at the end of the current clock phase.  This is what you desire.

The uploaded modified program has the following new features:

  • The stimulus clock of the 3 phase starts at 5000 Hz and can increment or decrement this frequency by 2.0008 Hz.
  • It starts a UART communication at 115.2 Kbps 8N1.  Using a Terminal program 
    • An input  '-' will decrement the stimulus frequency by 2 Hz.
    • An input '+' or '=' will increment the stimulus frequency by 2 Hz.
  • The UART comm will compute report the current stimulus frequency.
Len
"Engineering is an Art. The Art of Compromise."

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Luis,

I've tested my project that alters the frequency with a '+' (or '=') or a '-'.

I incremented the frequency by about 2Hz with each press.  Here's a scope plot with the frequency up to 5.500Hz

Len_CONSULTRON_0-1642168493073.png

Here's a scope plot when I decremented the frequency down to 4.500Hz

Len_CONSULTRON_1-1642168575847.png

I've re-uploaded the project just in case you are using a different version of the project.

 

Len
"Engineering is an Art. The Art of Compromise."
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luisji
Level 4
Level 4
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Dear Len

I copied your file, extracted, overwrited, runned, updated, builded, programmed into the psoc, adjusted to 115,000 bps the tera term, and tryed to move the frequency, without success.  I have been looking for my error, but I'm still without a clue.  See the image I've got:

luisji_0-1642716604399.png

As I assume your program is right, the problem most be on something related to the tera_term.   Trying to debug this I was seeing several parameters of Tera_term,  

luisji_1-1642716965626.png

but I have not found the error.   When Tera_term begins, I'm defining on the first screen that it work with the com3 port.  This doesn't shows more com ports, but options for terminal.  Maybe it be the problem. 

luisji_2-1642717621897.png

If I would select telnet, wich port should I select?

I have tried other configurations, but not the right one yet.  If you have any hint or clue, I'd be grateful for it. 

I have worked another details of the project, but this has to be solved to continue.

Thank you very much for your time and effort

Luis

 

 

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Luis,

I've uploaded a terminal program I've created and use with PSoC all the time.  It's VERY simple to use.   Find the COM port and "Open" it.  Then start typing in the window provided and the PSoC output appears on the same window.

 

Len
"Engineering is an Art. The Art of Compromise."
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Luis,

I'm not familiar with TeraTerm so I downloaded it.

To set up TeraTerm, I  started with "Setup/Serial port..."

Len_CONSULTRON_0-1642767805243.png

Select the COM port being used.  Mine was "COM5"  Note:  You can see by the "Device Friendly Name" that it is a Cypress named port.

Next select the "Speed".  In this case it is 115200.

The "Data", "Parity",  and "Stop bits" should be 8N1 respectively.

"Flow control" should be none.

The last thing is to select the button "New setting".  This opens the port and you are ready to input the '=', '+' or '-' characters to raise or lower the 3-phase frequency.  (As shown here)

Len_CONSULTRON_1-1642768128749.png

DO NOT USE the TCP/IP settings!!!  They don't apply to your situation.

Len
"Engineering is an Art. The Art of Compromise."
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Luis,

I finally completed the example code on how to design efficient ISR code to process multiple UART Rx ports.

FYI: Multi-UART-Rx-ISR-example 

Len

Len
"Engineering is an Art. The Art of Compromise."
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Dear Len

This was a message from a week ago, before the message from Dennis

==================

Good news!!  It worked!

The problem was that, in the version I downloaded of Teraterm (see next image)

luisji_0-1643021246202.png

First, is needed to set File - New connection...  in this window select serial port, then in the list select the cypress option.   After that, going to Setup - Serial port, do what you said about New setting, and then it worked!

luisji_2-1643024038799.png

The frequency on the osciloscope varies jumping between two values, I show this in the left - down part of this image.  It could be lack of precision of the osciloscope, but anyway, It works. The step, although not totally linear, is pertect under 1/100s 

Now I'll proceed to test the microphone, moving the volume of the speakers. 

The plan I have is this: 

luisji_1-1643022360572.png

Where the plan is to take into account two parameters:   The maximum in RMS and to be near 0 in the derivative of RMS ( I wrote slope instead of derivative)

Although now I see that Dennis (thank you Dennis), made a proposal, based on phase locked loop.  This has to be compared with what I said in previus paragraph, because I know that resonance will be between a range of frequency, but the optimal frequency is not fixed, as in a radio transmision is, and it varies not much, depending on temperature and maybe some other factors.  So I don't know wich model, if yours of Dennis's model could be better. What do you think?

In spite of I know that it is not the present part of the elephant yet, and is preferably you let this item for later, be it just for knowing that this will be a pendant item.   I'm a little worried about speed, as the program will have to sample mic signal, to generate the out signal, and to sample ADC from sensors.  So I think it will be needed to configure an interrupt clock for the program, in order to avoid using 'delay', for using the processor in the other tasks. 

================ AN IDEA FOR AN INTERRUPTIONS CLOCK IN PROGRAM

' task 1
if able_task1=1 then
if beginning = 1
endtime_task1 = time+ duration_task1
beginning = 0
endif
task1timeleft = endtime_task1 - time

if task1timeleft > 0 then
continue doing task (for instance, a signal = on )
else
end task1
able_task1 =0
endif
endif

[same for task2 and other with stated duration]

tasks without duration are simply executed

end program

' ==== interruptions
(each X time, a tic(interruption ) is obtaned from X clock)
time_number = time_number + tic
convertion to a serial number
convertion to ms - seconds - minutes - hours - days as needed

================

Maybe you have an example of this kind

.Then the question is:  What model is better?  Are they complementary in some way?

Thank you both for your time and knowledge

Luis

 

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luisji
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Dear Len

I have some doubts about it. 

Is it possible to get your institutional email?

Thank you

Luis

 

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luisji
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See attached, please.

 

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DennisS_46
Employee
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Luis:

This is a simple digital delay problem, that's what shift registers are for. PSoC5 Creator schematic is

DennisS_46_0-1642794311106.png

PWM1 divides 48MHz by 1600 to get 30 kHz. PWM 2 divides by 6 to get 5 kHz.
Shift Register 1 delays PWM2 output by 2 PWM1 clocks (1/3 of PWM2 cycle).
Shift Register 2 delays PWM2 output by 4 PWM1 clocks (2/3 of PWM2 cycle).
Output shown below:

DennisS_46_1-1642795039543.png
The output is at 5.0 kHz (200 usec period). The delay to the first SR edge is 66 usec, 1/3 of cycle.
To change the operating frequency, change ONLY PWM1. One step in the counter is approximately 3 Hz;
I believe this fits your requirement. The frequency step is not quite linear, but it is certainly monotonic, so
tuning with this waveform shouldn't be a problem. I found out a long time ago that phase-locking or
frequency locking with a oscillator that has >1/2 count of DNL (i.e., non-monotonic) does not work well.

As far as tuning, the normal phase-locked loop requires a phase detector (obviously). This is best done with a Set-Reset flip/flop, filter the output, run to a comparator. If high, decrement the divider in PWM1, if low, increment the
divider in PWM1. This saves measuring, decisions are simple, and the up/down single step acts as a sort of integrator/filter. One of the best references is the really, really OLD CD4046 PLL datasheet. It has guidance on setting PLL limits and gains and understanding the types of phase detectors. 

If you are working with continuous signals, this is easy. If with pulse signals then enable tuning only while pulse
is active (another hard-learned lesson from early sonar days).

For reference, I have been a PSoC apps engineer for over 21 years. It's been fun and there is always
a new problem to be found or to be translated from something else to PSoC.
Let me know how else I can hep.

---- Dennis

This approach DOES NOT WORK in PSoC4 because PSoC4 PWMs can only be clocked from a clock source, not
another block. If you want it in PSoC4, it will take some fun clock juggling.

 

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Dear Len

Please excuse my delay. 

I'm in charge of my 95 y.o. mom and today I went with her to make an all day tramit.  

Last night I was decided to put this to work, so I downloaded the Uterm software, tried to run it and surprise! it said I need to install .NET in order to work with it.  OK, I accepted, then the process tell me that I need to have an update of windows. OK, I'll install it, then it needs 700 Mb and stops telling me that I have not enough space.  So, I make the proper to delete some files, trying to save some useful files.  I made more than enough free space, then I proceed to install update, then It says that I need another updates, so I decide to look for a less demanding mini-terminal and suspend all updates and forget about .NET.   So I found a terminal named Termite, and hoping this doesn't eat my computer, I installed, then it didn't work with the psoc5.  Then I fall slept on my chair, so I didn't slept very well until two hours later I went to my bed.   Today I was thinking on taking this task again and I was happily surprised seeing that you has taken some extra time for helping me.  I'll follow your instructions and will tell you what happen then. 

Thanks again

Luis

 

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DennisS_46
Employee
Employee
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Luis:

I sent a PSoC5LP project to make the 3 phase generator. It works nicely.
My understanding is that you are driving one or more of the phase outputs to generate a signal in a pipe
and that you want that signal to be at the resonance of the pipe. One way to measure resonance is by
measuring amplitude. This method is not sensitive, the derivative of amplitude vs frequency is very low
near resonance. On the other hand, the derivative of phase vs frequency is at maximum at resonance, so
it is much easier to find resonance. If you want to talk through this problem, send your phone number
to my corporate email: dennis.seguine@infineon.com.
---- Dennis

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DennisS_46
Employee
Employee
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Len:

Send your phone number to dennis.seguine@infineon.com so we can chat and work
on the best way to support Luis.

---- Dennis

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