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PSoC™ 5, 3 & 1 Forum Discussions

Anonymous
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I have a fairly complex project that uses a PSOC to control a CRT vector display.  I recently started having trouble with a section that previously worked as expected.  I've tracked it down to an SR flipflop that seems to not behave properly.  I've deleted everything else in the project, so the attached project is just a flip flop with a constant 1 level on the S input and a constant 0 level on the R input.  The output of the FF is fed to an AND gate with a constant one on its other input.  The pin which is driven by the AND gate shows zero, which suggests that the FF is outputting zero.  If I change the gate to an OR gate, the pin outputs one, as you would expect. (So the pin appears to work properly.)  Can anybody tell me what's happening here?  If I completely recreate this in a brand new project, it works properly, which is nice to know, but I'm hoping I don't have to recreate my entire project.  Perhaps that's the answer though.  Does this "project rot" occur in PSOC?

Thanks in advance for any answers.

- Mike

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1 Solution
Anonymous
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Hi Mike,

In the project, Timer_Clock, that drives the SR flip flop, is not enabled. You can enable the clock either in .cydwr->clocks or using an API Timer_Clock_Start().

-Rajiv

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9 Replies
Bob_Marlowe
Level 10
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I am quite sure that the fitter optimized-out the RS-FF. The inputs do not change in your project.

Try to use a contol register connected to the S and R inputs, so the fitter will not "know" the signal.

Bob

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Anonymous
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Bob,

Here's a new project, with Control Register, same problem.

thx

Mike

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You still have a logic const at the FF, the result is predictable even for the fitter. Use a two bit control register and connect both outputs to R and S of the FF

Bob

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Anonymous
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Bob,

Although the input to the FF's Reset is a constant zero, the logic depicted should initially be zero until the control register is written with a one, at which point the output should be one.  Are you saying that PSOC Creator will create "optimizations" that don't conform to the design if there's a constant anywhere in the design?  (There was no constant in my original logic, I was just trying to reduce this to the simplest expression of the problem.)

I'm away for a couple of days, so I can't experiment further until Friday, at which point I hope to get to the bottom of this.

Thanks for your help!

Mike

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Anonymous
Not applicable

Hi Mike,

In the project, Timer_Clock, that drives the SR flip flop, is not enabled. You can enable the clock either in .cydwr->clocks or using an API Timer_Clock_Start().

-Rajiv

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SRFF.PNG

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pavloven,

I had similar issue with SR-FF, thinking that S and R inputs are "symmetrical" in nature - but they are not: Reset is always executed (Q=0), while Set executed only if R=0. Doh! - back to school...

/odissey1

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Anonymous
Not applicable

Thanks Rajiv!  I did wonder if something like that might be the case.  If I double-click on the clock in the schematic view, it's not obvious that it's disabled, but I do see in the design-wide resources "clocks" view that the enable box wasn't checked.  Thanks for solving my mystery.

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Anonymous
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You're welcome Mike.

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