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Hi,
I am working on SPI Slave communication using SPI Slave component on PSoC 5LP IC.
SPI Slave component is configured as 8-bit word size CPHA = 0, CPOL = 0 with 4-byte Rx and Tx buffers.
The first byte in the communication determines what will be transmitted afterwards, if bytes will be subsequently sent or received.
Any number of bytes can be transferred. The transmission will be terminated after the SS (Slave Select) signal deaserted, when the waiting time for the instruction byte is set again.
How is it possible to capture deaserting SS singal via SPI Slave component?
There is no flag in the Rx and Tx Status registers to capture the beginning or end of the communication specified by the SS signal.
Thank you
Milos
Solved! Go to Solution.
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Milos,
A simple solution is to add an a rising edge ISR on the SS signal.
See pic.
Len
"Engineering is an Art. The Art of Compromise."
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Milos,
A simple solution is to add an a rising edge ISR on the SS signal.
See pic.
Len
"Engineering is an Art. The Art of Compromise."