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Greetings all, i'm getting started with nRF24L01P IC, i'm able to get the values of the registers of the chip and save it on the Rx Buffer, my problem is when i try to know the "status" of the RxBuffer to know if it's full, not empty or overrun.
My RxBuffer size is 7 bytes, i'm only using 6, so SPI_ReadRxStatus must return me it's "not empty" i assume, all i got is a 0x0000, it's not even on the Rx return values, (it's on the TxStatus return values).
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PSoC 5LP
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Carlos,
it is always advisable to post your complete project, so that we all can have a look at all of your settings. To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
Bob
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You are using a buffer > 5 bytes. This activates the internal interrupt handling which removes the data from the FIFO and stores that in the buffer. Any Rx-status information are lost. You should use SPIM_GetRxBufferSize() API which does not return the size but the number of bytes received and stored in the buffer.
Bob
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Thanks for the answer Bob, didn't read that on the datasheet, your explanation solves my question. Also i found SPI_RX_BUFFER_SIZE, comparing it with SPI_GetRxBufferSize() must solve my issue, thanks again.
Carlos
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You are always welcome!
Bob
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I'm back, still having some problems with SPI, im having some glitches on the pSS line (about 0.5uS) specifically on nRF24_ReadMultipleRegister() and nRF24_WriteMultipleRegister() functions, i build it so there must be a silly error. I attach the logicdata file of the logic analizer (i'm sampling at 8MHz, SPI is 2MHz), the psoc proyect, a image with the problem and another one where i was able to write and read multiple bytes registers.
I haven't been able to find the problem, some days ago those functions were running well, i think my problem is a hardware one.
Thanks in advance
Carlos
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With this project i have no problems, nRF24_ReadMultipleRegister() and nRF24_WriteMultipleRegister() functions works fine, i have not found any differences, i don't know what can be the problem, any suggestion?
EDIT
It seems to be the System Master Clock, the non working project was 24 MHz, the working one is 48 MHz, now i think the problem is solved.
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The ss-line gets automatically de-asserted when the FIFO buffer is empty. This can be an unwanted behaviour when there are still bytes to be sent. A way out is to manage an slave select signal (pin) yourself, pulling it low at the begin of a transaction and releasing it to high at the end.
Bob
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polling SS line by myself seems to be the unique solution, did some tests and this problem are present with Tx or Rx buffers bigger than 4 bytes (software buffers), also found similar problems in old post here on the forum, the way i solved (without polling SS myself) is increasing the cpu freq., SPI@2MHz and CPU@48MHz, but if i want the cpu running @24MHz, what SPI clock must i use? 500 KHz? any rule of thumb?
Thanks for the help here and in other questions i did.
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Difficult to name a clock speed. Running at 48MHz will give the CPU more time to act, specially shoveling the bytes into the SPI FIFOs before they get emptied by the hardware.
Again: easiest will be to maintain an own ss-line that is held low during a complete transaction, not much overhead.
Bob