Problem with SPI-Logging, 2 Slaves receive alternately

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Anonymous
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Hello community,

i want to use the PSoC for logging SPI-Data and need some help.

First i simulate with another PSoC 5lp a simple Datatransfer from PSoC to SRAM "23LC1024". (Master_Transmission.zip)

Next i designed on the 2nd PSoC-5LP a Datalogger with two SPI-Slave Blocks and one SPI-Master Block. (SPI-Logger.zip)

The First PSoC transmit 100Bytes (0x1,0x2,0x3,0x4,0x5.....0x64   Diagram1&2) and the 2nd PSoC catch them and store them in another SRAM "23LC1024". (Diagram3) (The first 4 Byte are InstructionByte for the SRAM)

Diagram 2
Diagram2.PNGAfter a timeroverflow the PSoC-Datalogger load all Data from the Flash and send them to the computer, where the Data can be displayed with "Putty".(Diagram5)

Its important that i get all transmitted data, thats the reason i use two Slaves alternately. So the 2nd Slave can receive the next data, while the 1st Slave is busy with storing them in the Flash. That was my last idea to hold the Timing without losing data. (Master Clock = 2Mhz / Logger-Clock = 16Mhz)

Diagram 1

Diagram1.PNG

Diagram 3

Diagram3.PNG

The Problem is the 2nd Slave-Block respectively the receiving/Bufferswitch technique behind this. You can see in Diagram 3, that the first 20 Byte are correctly received and transmitted. But the next 20 Bytes and all other Bytes from the 2nd Slave are wrong.
Should be: 0x11,0x12.....0x24

Actually is: 0x32,0x41,0x51,0x61....0xe1,0x2,0x12,0x22,0x32,0x42,0x52,0x62 (Diagram 4 & 5)

Diagram 4

Diagram4.PNG

Diagram 5

Diagram5.JPG

My question is, whats wrong and how can i catch the right transmitted data correctly with both Slaves in the right order.

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1 Solution
Anonymous
Not applicable

Hi Rajiv,

your guess was right, my switch technique with two Slaves was not fast enough. I tried to store 100 Bytes but nevertheless i got losses in the reception. The reason for the "brocken" Bytes in the secound transmission was an asynchronous time-offset.

I have changed the logic to one Slave again and add some logic-gates to switch between the two storage-DMAs (look at Circuit Diagram). This techniqe was the solution for the Problem because the switching-Time is much faster ~2µs. (look at Timing Diagram)

Now my PSoC catches all transmitted Bytes without losses.

Nevertheless thank you for your advice.

best regards

Edward

Circuit Diagram:

Fin_Schaltung.JPG

Timing Diagram:

ISR-DMA-SWITCH-TIME.jpg

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