Parallel bus interface, but as a slave?

[david-given]

I wish to use a PSoC5 as a peripheral to another MCU (in this case, a HD64180). This uses a parallel memory 80-type interface (sixteen address lines, eight data lines, /ME, /RD, /WR).

While I'm aware of the EMIF component, this is the reverse of what I want to do --- EMIF allows the PSoC5 to be the bus master, controlling a slave memory peripheral. I want to do it the other way round, where the external MCU is the master and the PSoC is the slave. I know the logic to do this myself is pretty straightforward, but are there any standard components to do this for me? It seems like a common use case and there are some subtleties I'd like to avoid running afoul of.

Anyone know of anything?

Thanks!

[Aashita_R]

Hi @david-given ,

We would suggest a way to do this is -> For a memory to work, the address should be latched on the bus and then a wait signal would be there from HD64180 for PSoC to wait  sometime after address latching. You can use level-triggering of interrupt for this.

Also, the GPIOs should function as bi-directional since the data transfer would be bi-directional. However, there is no such component that would perform reverse of EMIF that would implement your application. You would have to proceed in a modular method. Hope this would have provided you some pointers.  Please feel free to add here in case of any further query. 

Best Regards,

Aashita

[BiBi_1928986]

Hello.

You'll want to watch this video on PSoC GPIO clock cycles.
C++ vs Assembly vs Verilog. on Vimeo

To my knowledge, there is no slave EMIF equivalent as a standard PSoC component.  There may be a custom component floating around somewhere, but chances are, it's not a HD64180 bus.

BTW (a comment, not an attack), you may confuse some people by mentioning HD64180 has a "80-type" bus.  That's generally interpreted to mean the 8080 processor bus, which has a multiplexed address/data bus.  The HD64180 has a Z-80 non-multiplexed bus.  And yes, 8080 and Z-80 have 16-bit address and 8-bit data bus.  While HD64180 has up to 20 address lines (depending on package).  But, let's concentrate on 16 address lines for now.

At work, I did the same thing as your project several years ago (I can not share code).

The first project was with 4MHz Z80 (same bus as HD64180 with refresh turned ON).  I replaced an obsolete EPROM with PSoC 5LP (plus a few new pcb features).  Code was done in assembler, interrupts were not used.  I did not need to insert wait states.

The second project PSoC 5LP replaced a UART/counter chip on a MC68000 pcb.  UDB to the rescue.  I setup UDB registers that 68000 could read directly while PSoC polled/refreshed the registers.

I mentioned the 68k project because it can perform a read-modify-write cycle without de-selecting chip select in between the read and write strobes.  The HD64180 has refresh cycle turned ON by default.  If software turns it OFF, HD64180 can also perform a read-modify-write cycle without de-selecting chip select.  So, don't count on chip select to toggle for each read and write cycle (in your implementation).

I'm sure you'll find this project interesting and frustrating.
Good luck with your project.

[david-given]

Re 80 bus: whoops! You're quite right. I assumed the wrong thing there. Does the Z80-style bus have a name of its own or is it the same as the 68000 bus?

Thanks, that's helpful. What I actually want to do is to emulate a UART --- sort of --- so I'm dealing with the I/O bus, which means I don't need to worry about refresh cycles (and has sixteen bit addresses, although I only care about eight). According to the 64180's manual the bus interface is really simple. What I was planning on doing was using a small chunk of verilog to do the address decode and connect the data pins to a set of control or status registers depending on address and whether the operation is a read or write. However, my verilog isn't great and I've never dealt with bidirectional pins before; I assume they're exposed as inout connections which I can set to Z to reading or 0/1 to write. Can you expand on the use of UDBs?

Also, unrelated: I got a message from the forum system saying 'You accepted a reply to a topic you are following as a solution!'... which I certainly didn't. I suspect moderator involvement, but it's rather unnerving.

[BiBi_1928986 · Accepted solution]

Hello.

Oddly enough, most datasheets only refer to the 80-type bus (address/data multiplexed) or the 6800-type bus (non-multiplexed).  Yet, there are so many non-multiplexed bus's that are not compatible with each other that they don't fall into those 80/6800 categories.  Oh well.  Just refer to the 64180 bus as, the 64180 bus.  FYI, the 68k has non-multiplexed address/data bus, but very different control lines from other processors.  Nothing unusual, just different.

Your approach is exactly as I did it.  Decode/control, status/control registers.  Well, as my FPGA colleagues helped me do it.  With the component library available today, you can probably do the logic design without entering into the Verilog world.  It's an option if you need it.

Depending on 64180 bus speed, you might need to insert wait states.  I'd plan for it.  The 64180 can be clocked pretty fast these days.

If you decide to use PSoC interrupts, be aware the PSoC ARM burns off 12 (min) to 20 (max) clock cycles to get into an ISR.  And just as many cycles to exit the ISR.

Yeah, I saw the solved status flip too.  Mistakes happen.