Level 2
Level 2

PWM maximum output frequency and register programming

Hi

I am a EE student and i just got my first job and i need to use Psoc eventually for monitoring a motor.

first ,if someone have some tips how to learn better the Psoc 5 world and embedded systems for a newbie i would really apprentice it.

question 1 :

I find it difficult to understand what are the PWM limitations.

i played with the component and i found out that at  - 16 bit resolution , at clock of 12.5 MHz, i got out put frequency of a 183 Hz.

i used clock of 12.5 MHz because that is the highest frequency  that get build without a warning. (i did used higher clock frequency's but the output did not change, measured by scop).

• there is a way to generate higher clock frequency's ? maybe via the firmware?

question 2 :

I read the the Clock section at Architecture_TRM  and i saw a lot of Macro's, there is a way to program via those Macro's? is it a pathway to program the register's directly?

im asking that question because my boss told me that via complete control  of the register ill get better results.

• is it the right way to work with Psoc? or that the Giu and the basic API's are the optimal way?

thank's

Michael

1 Solution
Level 9
Level 9

Re: PWM maximum output frequency and register programming

Michael,

Welcome to the world of EE and to the Cypress Microsystem PSoC!

Question #1.

With a input clock of 12.5MHz and a maximum divisor of 65536 (16-bit), you will receive a PWM clock of 190.735 Hz.  You already knew that.

The 16-bit PWM component in Fixed Function (FF) Implementation can handle an input clock of 80MHz.  The UDB Implementation of this 16-bit PWM can only handle 40MHz.  If you use the FF implementation, at 79MHz / 65536, your resultant frequency is 1220.7 Hz.  Probably still not what you are looking for.

Why do you need 16 bits of resolution? I've developed motor control circuits before.  Normally 8-bits are sufficient for most applications.  If you need more than 256 period counts (8 bits) consider using the 16-bit PWM with only 1000 period counts.  Therefore a 12.5MHz clock input can give you 12.5KHz clock output.

Note:  You can get more than 12.5MHz for a clock input to the PWM.  The reasons you are probably receiving Application Build errors is that you need to select your clocks sourcing correctly.   To do this, you need to use the Clock Editor.  See pic below.  You can see that

• IMO is set to 3MHz +/- 1%.  This is the primary clock for your system.
• I set the PLL_OUT frequency to 79MHz.
• I set the MASTER_CLK to PLL_OUT (=79MHz)
• The BUS_CLK is sourced by the MASTER_CLK and I set the divider to 1 (=79MHz)

With these settings I then assign my input clock to my PWM component (FF implementation) to the BUS_CLK.  This will build correctly.

Question #2

Unless you really know what you're doing, direct register access is ill-advised.

Most embedded CPUs you are familiar with have dedicated peripherals.  With these dedicated peripherals, they have dedicated registers to control them.  With these registers you have a limited set configurations allowed.

What Cypress chose to do is to make the most of the peripherals non-dedicated and user-configurable.  If you're familiar with what is commonly called PLDs (Programmable Logic Devices), then you will understand that the connections inside the PSoC are VERY CONFIGURABLE!   Cypress chose to create components for the user that allows the user a high degree of latitude of inter-connectivity between components.   This allows the user to create very sophisticated HW state machines that require minimal SW intervention to operate.  This can be a significant performance advantage above less sophisticated CPUs.  If the user can make use of the 24 channels of DMA available, it is possible to be even less SW dependent to further increase the performance of the system.

Because of this very high-level of configurability, the internal registers of the PSoC can be very confusing.  I would advise that you use the components that the PSoC offers to configure your peripherals.  I recommend for now that you don't modify the macros provided.  The component definitions and macros provide the SW "abstraction" that SW experts desire.  This is so that SW can be more portable and shareable between PSoC applications.

If the PSoC becomes your "go-to" CPU for projects (like it is with me), then I would recommend studying the PSoC components and the Architecture TRM for further understanding of how the PSoC operates.

I am creating advanced PSoC control by using the PSoC registers directly when needed.  But if a component does what I need, I favor using it and its API interfaces.

I hope this gets you a good start.

Len

Len
"Engineering is an Art. The Art of Compromise."
15 Replies
Level 9
Level 9

Re: PWM maximum output frequency and register programming

Michael,

Welcome to the world of EE and to the Cypress Microsystem PSoC!

Question #1.

With a input clock of 12.5MHz and a maximum divisor of 65536 (16-bit), you will receive a PWM clock of 190.735 Hz.  You already knew that.

The 16-bit PWM component in Fixed Function (FF) Implementation can handle an input clock of 80MHz.  The UDB Implementation of this 16-bit PWM can only handle 40MHz.  If you use the FF implementation, at 79MHz / 65536, your resultant frequency is 1220.7 Hz.  Probably still not what you are looking for.

Why do you need 16 bits of resolution? I've developed motor control circuits before.  Normally 8-bits are sufficient for most applications.  If you need more than 256 period counts (8 bits) consider using the 16-bit PWM with only 1000 period counts.  Therefore a 12.5MHz clock input can give you 12.5KHz clock output.

Note:  You can get more than 12.5MHz for a clock input to the PWM.  The reasons you are probably receiving Application Build errors is that you need to select your clocks sourcing correctly.   To do this, you need to use the Clock Editor.  See pic below.  You can see that

• IMO is set to 3MHz +/- 1%.  This is the primary clock for your system.
• I set the PLL_OUT frequency to 79MHz.
• I set the MASTER_CLK to PLL_OUT (=79MHz)
• The BUS_CLK is sourced by the MASTER_CLK and I set the divider to 1 (=79MHz)

With these settings I then assign my input clock to my PWM component (FF implementation) to the BUS_CLK.  This will build correctly.

Question #2

Unless you really know what you're doing, direct register access is ill-advised.

Most embedded CPUs you are familiar with have dedicated peripherals.  With these dedicated peripherals, they have dedicated registers to control them.  With these registers you have a limited set configurations allowed.

What Cypress chose to do is to make the most of the peripherals non-dedicated and user-configurable.  If you're familiar with what is commonly called PLDs (Programmable Logic Devices), then you will understand that the connections inside the PSoC are VERY CONFIGURABLE!   Cypress chose to create components for the user that allows the user a high degree of latitude of inter-connectivity between components.   This allows the user to create very sophisticated HW state machines that require minimal SW intervention to operate.  This can be a significant performance advantage above less sophisticated CPUs.  If the user can make use of the 24 channels of DMA available, it is possible to be even less SW dependent to further increase the performance of the system.

Because of this very high-level of configurability, the internal registers of the PSoC can be very confusing.  I would advise that you use the components that the PSoC offers to configure your peripherals.  I recommend for now that you don't modify the macros provided.  The component definitions and macros provide the SW "abstraction" that SW experts desire.  This is so that SW can be more portable and shareable between PSoC applications.

If the PSoC becomes your "go-to" CPU for projects (like it is with me), then I would recommend studying the PSoC components and the Architecture TRM for further understanding of how the PSoC operates.

I am creating advanced PSoC control by using the PSoC registers directly when needed.  But if a component does what I need, I favor using it and its API interfaces.

I hope this gets you a good start.

Len

Len
"Engineering is an Art. The Art of Compromise."
Level 1
Level 1

Re: PWM maximum output frequency and register programming

Hello,

I have the same question. I just looking for the best suitable controller for my new design. The implementation should be not to complicated because my time is limited.

My system is running with 1MHz. Can I use the PSOC for this application and reach 1MHZ PWM Output or is a FPGA the better choise?

Thanks for you help

Patrick

Level 9
Level 9

Re: PWM maximum output frequency and register programming

Patrick,

Is there a need to run a PWM at 1MHz?  Most motor control circuits can run at 10KHz or above to get out of the audible range.  Note: Controlling most motor circuit PWM in the audible range (200 Hz to 10KHz) may result in the user hearing the PWM carrier.

Are you creating a DC-DC power control circuit?  Or are you using 1MHz as a carrier frequency?

Here's a good "rule-of-thumb" to determine the input clock to a PWM:

PWM_FREQ = IN_CLK/(1<<BITS_RESOLUTION).

therefore ->     IN_CLK = PWM_FREQ * (1<<BITS_RESOLUTION)

An example:

PWM_FREQ = 1MHz

BITS_RESOLUTION = 8

Then IN_CLK = 256MHz !!!  Not practical.  Although you can use an FPGA, your input clock is very high and prone to radiated EMC emissions.

Len

Len
"Engineering is an Art. The Art of Compromise."
Level 1
Level 1

Re: PWM maximum output frequency and register programming

Hello,

thanks for your answer. Yes, I will create a DCDC-power converter and 1MHz is the switching frequency.

Yes, the high frequency is the challenge but many other universities solve this issue.

Level 9
Level 9

Re: PWM maximum output frequency and register programming

Patrick,

Commonly, DCDC converters use a higher PWM frequencies to lower the ferrite content in transformers and chokes.

I'm not an expert of DCDC conversion techniques.  I'm aware of PWM output as a somewhat common approach.

I believe I have seen an alternate approach that doesn't require a PWM component.  It is a digital/analog hybrid.  Therefore the potentially excessive input clocks for a PWM approach is mostly avoided.

Are you designing a buck (step-down) or boost (step-up)?  I'll try to dig up a block diagram of a hybrid.

Len

Len
"Engineering is an Art. The Art of Compromise."
Level 9
Level 9

Re: PWM maximum output frequency and register programming

Patrick,

Here is a simulation circuit of a DCDC converter (buck-only) that takes 5V in and regulates to 2V out (max current = 1A).

It is a conceptual circuit using a P-channel FET.   (I used the FREE LTSpice simulator)

This is a work concept of a DCDC converter with a 1 MHz updating but doesn't use PWM.  Instead it uses a comparator to determine if the output is too low and it gates with the update clock.  Here's the simulation results @ 1A load.

Here's a TopDesign snippet of a circuit based on the simulated circuit above.

You may have to adjust some values or change the P-channel FET circuit a little but I think it might work. (It least based on the simulated results).

A Boost regulator will be modified to include a diode in the main current path.

I hope this helps.

Len

Len
"Engineering is an Art. The Art of Compromise."
Level 2
Level 2

Re: PWM maximum output frequency and register programming

Hi Len, first thank you very much for the elaborate answer, I really appreciate it!

For your question, I dont really need 16 bit PWM, I just needed to get the limits of that component.

I have another question:

since English is not my mother language, studying from reading is bit slower then watching, as well as that for understating some of it i need more background and examples , so i am looking for online courses.

but I am not sure if I am overshooting.

(The Psoc courses that available in Udemy are just covering the basics)

so if you are familiar with a course it will be great, or if you can give me some guidelines for what to look for in a course.

thank you again,

Michael

Level 10
Level 10

Re: PWM maximum output frequency and register programming

When your native language is German I could probably help you a bit (or a byte 😉

1st advise: Do not do register programming for PSoCs, use the provided APIs.

Bob

Level 2
Level 2

Re: PWM maximum output frequency and register programming

Dank herr! (here my knowledge in German end)

Level 9
Level 9

Re: PWM maximum output frequency and register programming

Michael,

I'm glad I was able to help to some extent.

PWM suggestions

Refer to my response to Patrick.   Your application is motor control.   If you are controlling a Brush motor, you can easily use a 7-bit resolution to give you a 0 to 100 resolution.  Brush motors are very usable to cruder controls because of all the motor factors.  These factors include, cogging torque, brush-to-armature friction, load variations and much more.  Having great resolution is rarely needed.

If you're using a brushless DC (BLDC) motor, your are effectively trying to simulate a sinusoidal waveform on each of three phases of the  motor coils.  This may require more resolution depending on its application.   If you are driving a load that varies, then a lower resolution is usually sufficient.  If you're driving a motor for a fairly steady load and need precision speed control, you might need a few more bits of resolution.

Target your PWM output frequency to be about 10KHz.  Start your design with 0-100% control using 7 bits of an 8 bit PWM.  This will require an input clock to the PWM of 1MHz.  Very practical on the PSoC.

If you find you need more resolution, double it by using the 8 bit PWM from 0 - 200.  You will need to change the input clock to 2MHz.

If you find you need more, you will need to change to the 16-bit PWM and increase your input clock accordingly.

In general, if you have a good command of the C Language, this should be sufficient.   RARELY do you need to know direct register calls.  The C compiler with PSoC Creator is VERY GOOD!   Using the Cypress defined components are the preferred interface to the peripherals.  The compiler and Application Build process handles most if not all of the low-level interface to the internal registers.

The UDEMY courses only cover ARM-specific register details.  This course appears to be targeting compiler-designer experts who have to know how to properly control the ARM registers to operate a reliable system.   The PSoC5 (and PSoC4 and PSoC6) use the ARM architecture but the compiler and component environment buffers users like you and me from much of the low-level design knowledge.  This makes our job much easier for 99% of the work we need to do on the PSoC.  Note:  the UDEMY course will only cover the requirements and registers that apply to the ARM sub-system architecture.  The PSoC ARM represents only maybe about 10% of its IC.  The peripheral sub-system is very sophisticated and is not covered in the UDEMY course.  The PSoC Register and Architecture TRMs will cover this information.

I'm not trying to discourage you from learning what is going on underneath your application code.  I learn these details when I need to program at the register level by analyzing the C and assembly code generated.   I recommend in-depth learning.  Be careful.  Do not try to "eat the elephant" all at one-time.

English as a Second Language

I applaud that you have a command of English.  Given your occupation, English has been the standard for many years.

Let me end this discussion with this thought:

What do you call a person that can converse in TWO languages?    Bi-lingual.

What do you call a person that can converse in THREE languages?  Tri-lingual.

What do you call a person that can converse in only ONE language?  ...   American.

Len

Len
"Engineering is an Art. The Art of Compromise."
Level 2
Level 2

Re: PWM maximum output frequency and register programming

Thank you for the useful information and encouragement! i will not eat the elephant in one time

By the way i talk with my "boss" and he explain me what is the final product that i will have to design which is real time control system.

he guided me to use PWM and ADC\DAC for monitoring the information.

thanks again,

Michael

Level 9
Level 9

Re: PWM maximum output frequency and register programming

Michael,

You're welcome.  I've been a HW (and SW) design engineer for over 36 years.  I've always found new things to learn and new ideas to try.  It's been a great ride so far!

For motor control circuits:  PWM and ADC (for current sensing) definitely.  DAC?  Now you've made me curious.

Len

Len
"Engineering is an Art. The Art of Compromise."
Level 2
Level 2

Re: PWM maximum output frequency and register programming

DAC, well its a rookies mistake

but if ill find a way to use it ill let you know.

I actually thought to use PWM and ADC for controlling a voltage (generate an interrupt if the compare value is higher or lower then a fixed value that i choose) but i think that ill find more efficient way for it. (maybe using the VFD or other component from the power supervision family)

can you explain me how to use PWM and ADC for sensing a current?

thank you

Michael

Level 9
Level 9

Re: PWM maximum output frequency and register programming

Michael,

The circuit I provided is 100% HW once it is SW initialized.

I believe you talking about using a PWM (@ 10MHz) to modulate the output and using an ADC to read the output voltage and make corrections to the PWM duty cycle.  Hmm.  This is ill advised.

As indicated earlier, a PWM with an update rate (period) @ 1MHz and even only using 8-bits means that your input clock to the PWM component needs to be 256MHz which is not achievable on a PSoC.

Using a ADC is a nice idea but sampling the output voltage fast enough to be responsive to a highly transitory load will be beyond challenging.  It will be impractical.   If your application also processes other tasks, then you'll find more unexpected SW delays.

Both the reasons listed above is exactly why it is common to use a HW-driven feedback loop instead of a SW feedback loop.

PWM is only used to drive the output.  ADC is used for current sense.  Refer to the circuit snippet below.  R_cs is a very low-ohm resistor.  Chose a value low enough to minimize voltage loss (minimizing efficiency loss) while high enough to see a voltage drop large enough for your ADC to see the maximum current and above the noise floor.

Example:   Set the ADC sense range to +/- 0.128V for a 1A draw.   Therefore R_cs = 0.128V/1A = 0.128 ohm.  At 1A, this resistor will drop 0.128V.

Len

Len
"Engineering is an Art. The Art of Compromise."
Level 2
Level 2