PSoC5LP : Stop SysTick timer before Hibernate mode

[MiNe_85951]

Dear Sirs and Madams,

I am investigating the operation of SysTick timer.

I got a sample project of SysTick timer. Thank you.

PSoC5LP : How to use SysTick timer

I added hibernate mode to the sample project.

You can see that CyPmSeveClocks API switches the SysTick timer to IMO.

In other words, I understand that the SysTick timer does not stop on CyPmSeveClocks.

The CyPmHibernate API after CyDelay API has stopped the SysTick timer interrupt.

Do you know where the Systick timer interrupt is stopped in CyPmHibernate API?

Even if you check it with the debugger, you will not be able to check the SysTick timer interrupt when stepping.

Regards,

[Len_CONSULTRON · Accepted solution]

MaMi,

if you drop into CyPmHibernate() you go to CyPmHibernateEx():

void CyPmHibernate(void) 
{
    CyPmHibernateEx(CY_PM_HIB_SRC_PICU);
}

Once in CyPmHibernateEx() you will find in the beginning of the function where all ISRs are disabled.  At the exit of the function where they are re-enabled.

void CyPmHibernateEx(uint16 wakeupSource) 
{
    uint8 interruptState;
    /* Save current global interrupt enable and disable it */
    interruptState = CyEnterCriticalSection();
...
    /* Execute WFI instruction (for ARM-based devices only) */
    CY_PM_WFI;
...
    /* Restore global interrupt enable state */
    CyExitCriticalSection(interruptState);
}

Is this what you were looking for?

Len

[MiNe_85951]

Len-san,

Thank you for your comments.

SysTick timer interrupts stop in the hibernate API,

The timer clock that is the source of the SysTick timer has not stopped.

Understood above.

Have a nice Christmas and New Year.

Regards,

[Len_CONSULTRON]

MaMi,

In your design, what is the source clock for SysTicks?

In my understanding, in hibernate mode,  IMO, ECO and all clocks derived from them at turned off.

Here is a snippet from the PSoC5LP System Reference guide about preparing for Hibernation Mode.

PSoC® Creator™ PSoC 3/PSoC 5LP System Reference Guide,

Document Number: 002-28380 Rev. ** 41

Power Management

Low Power Usage

PSoC 5 devices will not go into low power modes while the debugger is running.

For PSoC 3/PSoC 5LP devices, the power manager will not put the device into a low power state if the system performance controller (SPC) is executing a command. The device will go into low power mode after the SPC completes command execution. The SPC is used by Flash API, EEPROM and DieTemp components. Please refer to the corresponding component datasheet for the more information.

Clock Configuration

There are a few device configuration requirements for proper low power mode entry and wakeup.

◼ The clock system should be prepared before entering Sleep and Hibernate mode to ensure that it will switch between Active modes and low power modes as expected.

◼ The CyPmSaveClocks() and CyPmRestoreClocks() functions are responsible for preparing clock configuration before entering low power mode and after waking up to Active mode, respectively. In general, CyPmSaveClocks() saves the configuration and sets the requirements for low power mode entry. CyPmRestoreClocks() restores the clock configuration to its original state.

◼ The IMO is required to be the source for the Master clock. So, the IMO clock value is set corresponding to the "Enable Fast IMO During Startup" option on the Design-Wide Resources System Editor. If this option is enabled, the IMO clock frequency is set to 48 MHz; otherwise, is set to 12 MHz.

Note The IMO value must be 12 MHz just before entering Sleep and Hibernate modes. The IMO frequency is set to 12 MHz by CyPmSleep()/CyPmHibernate() just before entering the specified low power mode (without correcting the number of wait cycles for the flash). The IMO frequency is restored immediately on wakeup.

◼ The PLL and MHz ECO are turned off once the Master clock is sourced by IMO.

◼ The Bus and Master clock dividers are set to a divide-by-one value and the new value of flash wait cycles is set to match the new value of the CPU frequency. Refer to the description of the CyFlash_SetWaitCycles() function for more information.

The 1 KHz ILO must be enabled (it is always enabled by default, regardless of the selection in the Clock Editor) for all devices for correct operation in Sleep and Hibernate low power modes. It is used to measure the Hibernate/Sleep regulator settling time after a reset. During this time, the system ignores requests to enter these modes. The hold-off delay is measured using rising edges of the 1 kHz ILO. The terminal count is set by the Sleep Regulator Trim Register (PWRSYS_SLP_TR). Caution Do not modify this register. Refer to the corresponding device Registers TRM for more information.

The 32.768-kHz external crystal oscillator (32kHzECO) provides precision timing with minimal power consumption using an external 32.768-kHz watch crystal. The oscillator’s power mode during device’s Sleep mode configured by the CyXTAL_32KHZ_SetPowerMode() function. By default, oscillator runs in the high power mode.

Calling the CyPmSaveClocks() function will modify device clocking configuration. As a result, any component that relies on clocking should not be used until calling the CyPmRestoreClocks() function, which will restore the original clocking configuration. For information on component clocking requirements, refer to the corresponding component datasheet.

Hopefully this might explain your situation.

Len