PSoC5LP EMIF with multiplexed address-data lines to LAN9252 chip

Hvdbrand · ‎Nov 12, 2021

Dear all,

We are looking on using a EtherCAT ESC chip (LAN9252) together with a PSoC5LP.

The LAN9252 chip can be connected over a host bus interface (chapter 9 of the datasheet).

I would prefer to connect it to the PSoC in multiplexed mode in which 16 lines are used for the address and data, with a single line to latch the address.

I have looked into hooking this up in the PSoC5LP and found the External Memory Interface (EMIF).

However, looking at that component I saw no configuration to multiplex the address and data lines.

Is there any standard component that could provide multiplexed address/data lines towards the LAN9252 chip?

It might be possible to create a circuit (inside or outside PSoC) to perform the latching, but I would rather not go that route.

Any thoughts?

Len_CONSULTRON · ‎Dec 06, 2021

Hugo,

Len, would there still be a reason to consider SPI over EMIF with indexed mode?

Humm... Theoretically, EMIF Index should allow for a faster data rate. SPI 16-bit has a top end of 16Mbps.

I guess if you can spare the pins EMIF should give you better performance.

Len
"Engineering is an Art. The Art of Compromise."

View solution in original post

PSoC5LP EMIF with multiplexed address-data lines to LAN9252 chip

PSoC5LP EMIF with multiplexed address-data lines to LAN9252 chip

Re: PSoC5LP EMIF with multiplexed address-data lines to LAN9252 chip