PSoC5LP EMIF with multiplexed address-data lines to LAN9252 chip

[Hvdbrand]

Dear all,

We are looking on using a EtherCAT ESC chip (LAN9252) together with a PSoC5LP.

The LAN9252 chip can be connected over a host bus interface (chapter 9 of the datasheet).

I would prefer to connect it to the PSoC in multiplexed mode in which 16 lines are used for the address and data, with a single line to latch the address.

I have looked into hooking this up in the PSoC5LP and found the External Memory Interface (EMIF).

However, looking at that component I saw no configuration to multiplex the address and data lines.

Is there any standard component that could provide multiplexed address/data lines towards the LAN9252 chip?

It might be possible to create a circuit (inside or outside PSoC) to perform the latching, but I would rather not go that route.

Any thoughts?

[Yugandhar]

Hello, 

There is no standard component which performs latching.

PSoC5 has digital comparator and status register components from which you can easily build the required latches you want. Please refer to the below thread.

https://community.infineon.com/t5/PSoC-5-3-1/How-can-I-make-a-programmable-latch-16-8-bits-Is-there-...

Thanks,

P Yugandhar.

[Hvdbrand]

Hi,

Thanks for your reply.

I looked into the example, but it assumes that the digital lines that need to be latched are available signals.

When I use the ExtMemory Interface the address and data lines are not made available as signals. Therefore, it looks like I cannot feed the address and data lines through a latch and multiplex the signals inside the PSoc digital circuitry. Therefore, if I were to go that route I would need to multiplex on the PCB.

I might be missing something here, so please correct me if I am wrong.

Best wishes,

Hugo

[Yugandhar]

Hello, 

Could you please let me know your design ? In PSoC5 Device, you can use the Digital multiplexer if required for your design. 

Thanks,

P Yugandhar.

[Len_CONSULTRON]

Hugo,

I've attached a project as an example of 16-bit Address and 16-bit Data muxing.

It is NOT complete (the state logic for talking to the LAN IC is not finished).  It is an example of how to mux the address and data.   The LUT (Look-Up-Table) is no implemented state logic.  I came up with a TopDesign to see if the PsoC5 has enough resources.

I should point out that the LAN IC is capable of SPI communication.  If you SPI this instead of the multiplexed Adr and Data it would be simpler and take fewer PsoC resources (pins and UDB blocks).

[Hvdbrand]

Thanks for the responses. Based on your replies I see that there is no way to directly do an ADMUX with the EMIF component. Len, thanks for showing me how to go about implementing the ADMUX.

The LAN9252 also supports an indexed mode in which there are both data lines and address lines. The number of address lines is limited. Therefore, 8 bit address, 16 bit data, and 3 control lines suffice for the indexed address mode. This indexed address mode does allow me to use the EMIF component.

It seems I have sufficient pins to implement this approach.

Len, would there still be a reason to consider SPI over EMIF with indexed mode?

[Len_CONSULTRON · Accepted solution]

Hugo,

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Len, would there still be a reason to consider SPI over EMIF with indexed mode?

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Humm...   Theoretically, EMIF Index should allow for a faster data rate.  SPI 16-bit has a top end of 16Mbps.

I guess if you can spare the pins EMIF should give you better performance.