Are there any plans to introduce new PSoC 5LP members with more package pins and 24 UDBs ?
Or alternatively to introduce PSoC 4200L 124-ball VFBGA with more UDBs ?
My problem is that I need more than 72 I/O pins available on PSoC 5LP and more than 8 UDBs available on PSoC 4.
My design needs more than 128 PT (product terms) to fit.
Try to optimize the design using PSoC4, with PSoC there is usually more than one way to "slice the cow".
Unfortunately, even my initial design does not fit into PSoC 4, it requires 130 PT and I still need to add a counter and terminal condition detection. I do not understand why PSoC 4 does not have 24 UDBs ! That would be excellent.
To understand some background - I want to eliminate external FPGA and save on the cost and PCB resources. But I need loads of UDBs !
I cannot post anything publicly.
Are there any plan to introduce higher pin count PSoC 5LP, please ?
We can hardly fit into TQFP100 and we still need more pins.
I just wonder, there are NC pins on TQFP100 pins 57 to 62, it they are GPIOs, that would help a lot.
The best would be a VBFGA124 or similar.
PSoC5 is becoming old, I doubt if Cypress will introduce any new parts. Can you use 2x PSoC4 parts instead?
PSoC 5LP is the only one with 24 UDBs.
If Cypress offers PSoC 4 with 24+ UDBs and 120+ pins, then I will go for it.
But not a second sooner.
PSoC 5LP is the only platform for long term growing large mixed signal projects. I also wish to have a PSoC 5XC series (for extended capability) or a PSoC59xx-series with more of everything. Processor speed is not a struggle at the moment. But soon I will reach the limits of analogs and digitals. PSoC6 is not a real mixed signal controller anymore. It is too restricted when it comes to analog and to flexibility. It targets projects, where processing power can overcome shortenings in the other areas. Without having the needed amount of ADCs and DACs for doing so. And PSoC 4 would force to build multi-chip systems, which are difficult to maintain regarding firmware updates and are also restricted in flexibilty, because hard wired connections between the chips are not freely programmable in comparison to a chip as we have with 5LP.
This is my opinion as a 5LP-user since 2015. By the way: I started my largest project with PSoC4 but switched to 5LP at a certain point.
For better understanding I will upload the internal schematic of this project.