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Hi,
We are using PSoC 5LP: CY8C5467AXI-LP108.
We have implemented waking up PSoC from hibernation using one pin (button push down). Now we want to add two more buttons, each will wake up PSoC from hibernation.
My questions are:
1. Should we assign all three pins to same port? What is the difference for assign the three pins to one port or different ports for interruption implementation?
2. What is the meaning for "Dedicated interrupt" checkbox in pin configuration? In my case, the checkbox is checked but greyed out, why?
3. To save interrupt handler, can I enable interruption for each pin, and connect all the interrupts to a NAND gate and still wake up IO PSoC?
Thanks,
Winston
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PSoC5 LP MCU
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- isr
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Winston,
I believe I can answer question 3:
3. To save interrupt handler, can I enable interruption for each pin, and connect all the interrupts to a NAND gate and still wake up IO PSoC?
You can use a single ISR handler code for all three interrupts. However in hibernation mode, the NAND gate you want to use is non-functional. The NAND gate would be a part of a UDB block and UDB blocks are powered down during hibernation.
This leads me in attempting to answer your question 1.:
In low-power modes, only certain PSoC resources can be used to wakeup the CPU.
Here is an excerpt from "AN77900 PSoC® 3 and PSoC 5LP Low-Power Modes and Power Reduction Techniques"
If you do assign all the wakeup pins to the same port you can easily use the same interrupt source for all three. See pic below. This appears to take care of question 3.'s NAND gate issue.
Now about question 2. ... There is some description in the "Pins" datasheet about it. I'm a bit confused by the description maybe it makes sense to someone else. Note: I've never used this feature.
"Engineering is an Art. The Art of Compromise."
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Winston,
I believe I can answer question 3:
3. To save interrupt handler, can I enable interruption for each pin, and connect all the interrupts to a NAND gate and still wake up IO PSoC?
You can use a single ISR handler code for all three interrupts. However in hibernation mode, the NAND gate you want to use is non-functional. The NAND gate would be a part of a UDB block and UDB blocks are powered down during hibernation.
This leads me in attempting to answer your question 1.:
In low-power modes, only certain PSoC resources can be used to wakeup the CPU.
Here is an excerpt from "AN77900 PSoC® 3 and PSoC 5LP Low-Power Modes and Power Reduction Techniques"
If you do assign all the wakeup pins to the same port you can easily use the same interrupt source for all three. See pic below. This appears to take care of question 3.'s NAND gate issue.
Now about question 2. ... There is some description in the "Pins" datasheet about it. I'm a bit confused by the description maybe it makes sense to someone else. Note: I've never used this feature.
"Engineering is an Art. The Art of Compromise."