MoPr,
| I have done exactly what you told. I played around with the buffer sizes to see if the position of the spikes matches the number of samples stored before writing. It matched that everytime. I tried 250, 500, 750, 1000 samples and the spikes occured at 250, 500, 750, 1000 samples. I even disabled the SD card writes to see if the voltage spikes disappeared and it did. |
You're doing excellent work in highlighting the source of the spikes. A simple SW change in the SD dump trigger has determined the source beyond any reasonable doubt. You were correct in your first assumption.
... I am not quantitatively sure how it affects the rise time. Is there a way to calculate rise time when only a series resistance is used? Addition of capacitance to ground will require a new iteration. I will include it in the next iteration.
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There is a quick rule for the rise time.
- Multiply the total series R times the total parallel C. This is the 'tau' of the exponential rise curve. One 'tau' time factor will have the signal go from 0V to 62% of VDD (5V in this case).
- Now multiply the 'tau' time value by 2. This is the 90% point in the rise time. Rise time is 'roughly' measured from 10% to 90% of 0V to VDD.
Could it be a termination issue? The PCB tracks are not impedance controlled and I don't have termination resistors. |
Signal termination is more of an issue when the wiring is longer (excess inductance 'L'). Excess 'L' can cause signal overshoots which can be a problem for the signals that are clocks.
Since you are using the 74LVC125A, if you were to place any additional R or C on the signal it would be on the signal output from the 74LVC125A.
Before you add any more Rs or Cs in the signal path, I may have another solution.
The spikes show up when you are simultaneously performing a read with the delta-Sigma ADC AND a SD write using the SPI comm. Solution: Avoid performing an ADC measurement when writing to the SD. Simple to say. Maybe harder to do.
Can you coordinate each ADC conversion to cause a 'pocket' of time where the dump of data to the SD can be accomplished between conversions?
The delta-Sigma ADC usually takes longer for a conversion. The SAR ADC can convert faster. Using the SAR ADC will create a bigger 'pocket' of time for the SD write.
If you need higher resolution, the delta-Sigma may be necessary.
When performing the SD write, faster is better (less need for a large 'pocket'). Therefore reduce the R and C of the signal path circuits and try to clock the SPI data at the faster rates tolerable. Using a scope, check the signal quality on both sides of the level translator to make sure there is no significant overshoot (or undershoot) to the signal.
I really doubt if you're drawing 100mA from this level translator. It's probably more like 50uA tops.
Len
Len
"Engineering is an Art. The Art of Compromise."
