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Hello Everybody,
I am trying to configure to use the low- pass filter with cutoff of 100Hz from a signal coming from a ADC DelSig. Sadly I am not getting the expected results. Has someone some example of configuration to filter block?
PS: I know that the signal coming from is ADC( passing by DMA) is correctly because I already tested it.
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PSoC 5LP
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What is it that you are expecting, and what is it what you are getting?
Did you try to use a buffer beween filter and ADC? How ist your ADC configured? Maybe post your complete project ("File/Create Workspace Bundle")...
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I uploaded my project as you had said. I am just expecting a simple lowpass filter. I configured as a 4th Order, but it can be 1st Order. The cutoff were configured to 100 Hz. You can see all the configurations of ADC in the project that I uploaded.
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I would consider increasing the sysclk frequency to 60MHz, that gives your interrupt handler some more processor time. 10k interrupts per second @ only 24MHz could be a bit tough.
Additionally I would suggest to use 4th or 6th order filter.
Bob
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Forgive my ignorance, but were could I configure the system clock? The only places that I saw to change the clock were in the Filter block and in the ADC block.
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That is no ignorance. Open the .cydwr - file (where you can set the pins), click on the Clocks tab and double-click on one of the clocks. In the opening window set the PLL-out to 60MHz.
Bob
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Ok, understood. I will try it! Is there any other configuration that can cause problems in my project?
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I didn't see any so far.
Bob
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I am getting a strange warning: Asynchronous path(s) exist from "\ADC_DelSig:DSM\/dec_clock" to "CyBUS_CLK". Should I be worry about it?
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When I try a signal with 5Hz frequency the output signal from ADC is reduced greatly. Why is this happening?
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Difficult to guess, no more facts to work on? Workspace bundle??
Bob
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What is the minimal frequency that psoc 5 can deal with? I said that this was occuring with 5 Hz, but the ADC output gradually decrease starting from 15Hz to 1Hz. Above this value the output from ADC DelSig works as expected. The only thing that I changed since last time is that I set the master clock to 70MHz.
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Daniel,
Which PSoC5 ADC? Delta Sigma or SAR? Can you post your complete project, so that we all can have a look at all of your settings? To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
Bob
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Bob,
I was making some tests and I forgot to set the same sample rate, but even when they are the same value I got some problems.
I am trying to develop a system to capture EMG signals ( eletromiographic signals ). Since this project is just a prototype, I am not worried to use the real EMG signals yet. To simulate small signals I am using Vin = 50 mV (with 100mV offset) and I am setting the frequency in range of 1Hz to 200Hz. At the moment I wish to develop the lowpass filter, with cutoff = 100Hz, however when the frequency < 15Hz the signal coming from the ADC is reduced ( even before been processed by filter). The pin called "teste" is just to verify the signal from ADC.
Daniel.
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"however when the frequency < 15Hz" Which frequency??? The ADC can of course work with DC signals.
Your DMA looks a bit different from what I use, you set
CyDmaTdSetConfiguration(DMA_1_TD[0], 1u, DMA_INVALID_TD, DMA_1__TD_TERMOUT_EN);
DMA_INVALID_TD means afaik that when the TD finishes the channel is done (no next TD) and must be started again. I would suggest you to use the dame TD in a loop, thus
CyDmaTdSetConfiguration(DMA_1_TD[0], 1u, DMA_1_TD[0], DMA_1__TD_TERMOUT_EN);
same applies to the other DMA-channel.
Your ADC-reference should be buffered.
To compensate for offsets you should think about to use external VREF for OpAmp and connect to proband's body.
Bob
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I don't see any problem using the ADC converter with AC Signals.
The main structure of this project I took from the example from PSoC Creator, including the DMA configurations. To include the DMA_1 (the second DMA block) configurations, I used the DMA Wizard from PSoC Creator. I will take a look at these configurations, but I don't have pretty much knowledge about it.
Could you give some example about the buffered ADC-reference? It still not very clear for me.
Daniel.
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Daniel, look into the ADC Datasheet for the explanation of the different VREF selections: Buffering needs a cap connected to a pin and ground and increases precision.
Bob
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Ok. So at first I would have to set to differential mode. Then I would have to configure the Vref to external on P0[3] or P3[2] pin. After that, I have to connect a capacitor to this pin and to the ground. All the other configurations I leave as they already are. Is that correct ?
I uploaded an image which I got from an example of Creator. Can you confirm that there they use the same principle of buffer on ADC? ( I did not understood the example for all)
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I cannot see on a picture the internal settings of the ADC.
When using a CY8CKIT-059 a bypass capacitor is already mounted at P0_3, so you may select that.
On ADC datasheet just look at page 13 and additionally the footnote.
Bob
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This picture is from the Filter_ADC_VDAC example from Creator. I will upload the project.
I already had looked in ADC DelSig datasheet, but I was in doubt about when to use each configuration.
Let's suppose that the P0_3 was chosen and the desirable Vref = Gnd. Then may I just connect P0_3 to Gnd? (Considering that bypass capacitor is already mounted internally on P0_3). Making this that you have said is different from setting Vref=Vss(internal Gnd)?
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When I was talking about Vref and GND I was talking about the OpAmp, not the ADC. I mean
Configure the OpAmp to have as second input.
Do not tie P0_3 to Gnd!!! This is the internal Vref braught out to a pin to have it stabilized.
When you use a CY8CKIT-059 there is already a 1µf cap connected to P0_3!
Bob
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Ok, things become pretty much clear when I saw the Filter.jpg.
I think that I got the main idea. Now I am going to try these tips that you said. If the circuit still does not respond as expected I will ask for more help. Thanks for the help!
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You are always welcome, Daniel!
Bob
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I made some tests I found where I was getting the wrong answer. I placed only the PGA and when the signal ( with offset ) had frequency < 20 Hz the output was getting pretty lower than expected ( gain=4, Vin = 100mV, Vout= NOT 400mV). I tried only Vref = Vss(internal) yet, but I think that even in this configuration It should works. Someone has some hint?
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Do you place a capacitor to the input of your PGA? This will build a high-pass (and block DC) together with the input resistance of the PGA. Please show your complete external connections.
Bob
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The VGA input is getting the raw input signal ( I am not using an external capacitor or a resistor for Vin).
Which value should I use for external capacitor?
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Please post your project you used for the PGA test
Bob
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Where do your 100mV come from and what exactly do you measure at the output pin? What is your measuring device? Scope? Multimeter?
Fact is that the PGA within the PSoC usually works fine, there are no known issues.
Can you draw a map Input Voltage versus Output Voltage
Bob
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I made more tests and I discover that the real problem (apparently) was the Scope I was using. When I changed it everything worked very good! Now the PSoC works as lowpass filter!
Thanks for all help!
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Hurrrahhhh!!!! ;-))
Bob