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I am trying to get a UDB based timer to reset when it captures a value, but nothing that I have tried has worked. Please take a look at the attached schematic capture and let me know what you think. I have tried a number of variations on this setup, but nothing has worked correctly.
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PSoC 5LP
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The datasheet is not clear on this but I suspect that either the reset pulse width is not wide enough,
1 clock or more, or there is a state condition that with a hardwired capture out to reset connection
the part just stays in reset.
Regards, Dana.
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Maybe I need to restart the component after reset?
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So, I have been doing a bunch of experimentation, and it still isn't working correctly. I added some flip-flops to make sure that the capture_out output is held high long enough to reset the timer, and I have verified that the additional circuit is working correctly using an o-scope, but now all of the captures are showing as the reset value, not an actual count. I have measured the reset frequency at 123Khz, and with a clock frequency on the counter of 64Mhz it should end up with a count of about 0xFFFF - 520 or so, but I am always getting 0xFFFF from the capture. Does the reset clear the capture register? It doesn't seem like it should, but again the documentation is not very clear.
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Thanks! I had exactly the same problem. I could fix it using two D flip flops in series.
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When you work with the UDB option and you need to reset after capture, you must select the option One Shot (Halt to Interrupt), in Run Mode. In this way the Timer restarts each time an interruption occurs.
Regards.
Mariano.