I have an existing design based on a PSOC5LP Cy8C5467 where we have had to change to a Cy8C5667.
This variant of the chip will not start up with a slowly rising power supply.
I am using a precision external 17MHz oscillator module as the system clock source. This oscillator is unstable for 5ms during startup which causes the PSOC to NOT boot. It can be solved with an external reset, but we already have product in the field.
The system will start reliably with the IMO internal oscillator OR with the external clock and the PLL disabled.
Unfortunately, the PSOC provides no safety mechanism for external clock, or the ability to program a higher reset threshold before coming out of initial power-up reset.
Does anyone know how to disable the PLL on startup, then enable it without the clocking wizard messing up all my subclock dividers? (ie I need a system clock of 60MHz, and for the wizard to calcualate my various sub clocks, but start up at 17MHz without the PLL)
eg. Compile with the PLL on, so the wizard correctly sets all my sub clocks, but then 'hack the compiled code' to disable the PLL, then start it after I run
// Enable low-voltage detect
// Wait till low-voltage condition no longer exists before continuing
while (CyVdRealTimeStatus() & 1) ;
PSoC5 LP MCU
Although, I've never had this problem, I can understand why this would be a problem in your application.
The PLL with PLL_OUT has a "ghosted" "Start on Reset". If you could deselect it this might solve your problem.
Here are potential solutions.
Make sure your PLL is configured as you need. However DO NOT clock your CPU on the PLL but on the IMO. (As shown above). Once you're up and running, test to make sure the PLL is "locked". Once locked, you can switch the source of the MASTER_CLOCK to be the PLL using the API call. Theoretically problem solved.
There are system API calls to control the PLL and MASTER_CLOCK in SW as a part of your application.
Therefore, you can bootup with the MASTER_CLOCK being sourced from the IMO. This will allow for the CPU to be running at minimum active power.
You can then set the PLL fractional values (p & q). You'll have to study the API call documentation to understand which values are allowed and how to calculate the required values for the PLL output you want.
Then enable the PLL startup. Once locked, switch the MASTER_CLOCK source to PLL and you should be good to go.
"Engineering is an Art. The Art of Compromise."