Hi,
I'm glad to see people are using another Great tool available: LTSpice!
I've worked with FETs before and understand the problem. The lower the Rdson the FET can provide the higher the input capacitance. This is because internally the FET is actually paralleling the equivalent of smaller higher Rdson FETs, They do so by elongating the Drain and Source junction which ends up elongating the Gate.
I'm assuming that you are using a "dumb" FET. By "dumb" I mean the FET IC is just the FET. "Smart" FETs have many other additional functions which include protection circuits and most importantly a FET gate driver. The FET gate driver is sized to drive the capacitance of the Gate without having the user worry about it. To the user, the input impedance can be driven with 1K ohm and the input capacitance is < 12pF.
If you're going to use a standard "dumb" FET, you may need a gate driver. You can construct a gate driver using a NPN/PNP pair such as the NXP PUMD2.
The datasheet for the PSoC5LP for Voh = Vddio-0.6V when driving 4mA load @Vddio = 3.3V Therefore the internal source resistance when driving the digital GPIO pin high is worst-case 0.6V/4mA = 150 ohms.
A fully discharged load capacitance (let's pick 25pf) acts like a temporary short. Therefore the initial surge current when driving the GPIO from 0 to 1 is 5V/150ohms = 33.3mA. This about 8x times more than rated current. However, the PSoC is designed to thermally take these surges currents all day.
The simulation plot below models the GPIO output with 150 ohm internal resistance a 1MHz pulse at 5V driving 25pF. The plot is the wattage of the 150 ohm resistance of the high switch (S1) which is the only consuming structure in the PSoC on the 0 ->1 transition. The single pulse is has an average power of 326uW. If I increase the number of pulses to 1 Million, (one second of operation) my average power remains the same. Since 326uW is about 1000x below 300mW for the device package, not much to worry about. The PSoC was designed to current surge to 33mA if needed. Also the instantaneous energy of any single pulse is 326pJ. I double this value because the power dissipation also includes the 1->0 transition and I'm still in the "safe-zone".
As predicted, the rise time is about 9.3ns.
If I increase C1 to 200pF, my rise time is now 66.6ns and my average power dissipation is 2.5mW which is 7.7x more power than with the 25pF cap. Additionally the energy S1 sees is now 2.5nJoules which is 7.7x higher. You might be able to get away with the additional average power increase but only Cypress can tell you if the internal instantaneous energy increase may damage the GPIO (S1 and S2).
I know I was a bit wordy, but hopefully this might give some insights to the design issue you are facing.
In summary, since you are exceeding the 25pF output drive capacitance, consider at least using a NPN/PNP driving pair external to the PSoC to drive the FET gate.
Len
