I have a question regarding PLD power draw, particularly digital blocks with a very slow (or no) clock.
I have an application I'm considering porting to PSOC, but before I do I'd like to hear what the consensus is about running PLD blocks in very low power designs.
The design needs to sleep for the majority of its lifetime as it is battery powered, and must last several years. the device wakes up roughly once every second for about 1ms, and should have an average power draw below 40uA.
I now want to extend the device to incorporate a receiver for a very low data-rate serial protocol. essentially the receiver device will send a wake signal to its micro, followed by a clocked data stream of about 2ms per bit (500 baud). Capturing the data is very easy. In my current micro implementation I sample the data with an interrupt triggered by the clock line. The problem with this is power. As it is currently I have to keep my micro awake for the entire duration of the data transfer (~100ms), which basically kills any aspirations I have for a lower power device.
I thought the project might be a good candidate for a PSoC, as I could use an SPI block or even a custom Verilog based block to capture the data, and wake my micro a fixed timeout period after the data has stopped.
My question is, will a psoc PLD block draw little enough current if it has a very slow (just the 2ms data clock line, perhaps a 32khz source for timeout...). Can I even have PLD blocks running in sleep modes? Would it be more effective to have the micro simply wake briefly every time the clock line activates?
