Own Verilog/UDB component with trigger input => what needs to be done when trigger is active?

RaAl_264636 · ‎Oct 18, 2021

Hi,

I'm creating a component which uses a rising edge trigger input. The component uses two states. In the first state, the inputs are saved and the internal state machine switches to the next state on trigger, does some calculation and then switches back to the first state.

I wonder if storing the values in the first state should always be performed, leaving the trigger event to only change the internal state or saving the inputs only when the trigger is detected. Currently I can't see no difference, but my experience with hardware description is quite low.
Maybe someone can give pro/contra for each approach?

Regards

RodolfoGL · ‎Oct 21, 2021

When using PI in the datapath, you can't do ALU operations, so you will not be able to do subtraction or addition. Refer to the Component Author Guide section 11.6.4.1 Datapath / Limitations of the datapath.

Parallel input into the datapath is limited. This restricts the ability to use the datapath where other
hardware needs to provide a parallel value. Alternatives to parallel hardware loading may be
possible. If enough cycles are available, then a value can be serially shifted in. If the CPU or DMA
can get access to the value, then they can write the value to a FIFO or register in the datapath.

You might need to use two dapatah and use a DMA to move the input data. Basically the flow would be:

1) Datapath0 captures the PI and load to the FIFO0

2) DMA triggers based on FIFO0 level. Transfer from Datapath0.FIFO0 to Datapath1.FIFO0

3) Datapath1 loads the FIFO0 to ALU

4) Datapath1 performs ALU operation - Addition or Subtraction. (A0 + D0) or (A0 - D0)

5) Result is available in the Datpath1.PO

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Own Verilog/UDB component with trigger input =&gt; what needs to be done when trigger is active?

Own Verilog/UDB component with trigger input => what needs to be done when trigger is active?

Re: Own Verilog/UDB component with trigger input => what needs to be done when trigger is active?

Own Verilog/UDB component with trigger input => what needs to be done when trigger is active?