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PSoC™ 5, 3 & 1

RaAl_264636
Contributor II

Hi,

I'm creating a component which uses a rising edge trigger input. The component uses two states. In the first state, the inputs are saved and the internal state machine switches to the next state on trigger, does some calculation and then switches back to the first state.

I wonder if storing the values in the first state should always be performed, leaving the trigger event to only change the internal state or saving the inputs only when the trigger is detected. Currently I can't see no difference, but my experience with hardware description is quite low.
Maybe someone can give pro/contra for each approach?

Regards

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1 Solution
RodolfoGL
Employee

When using PI in the datapath, you can't do ALU operations, so you will not be able to do subtraction or addition. Refer to the Component Author Guide section 11.6.4.1 Datapath / Limitations of the datapath.


Parallel input into the datapath is limited. This restricts the ability to use the datapath where other
hardware needs to provide a parallel value. Alternatives to parallel hardware loading may be
possible. If enough cycles are available, then a value can be serially shifted in. If the CPU or DMA
can get access to the value, then they can write the value to a FIFO or register in the datapath.

 You might need to use two dapatah and use a DMA to move the input data. Basically the flow would be:

1) Datapath0 captures the PI and load to the FIFO0

2) DMA triggers based on FIFO0 level. Transfer from Datapath0.FIFO0 to Datapath1.FIFO0

3) Datapath1 loads the FIFO0 to ALU

4) Datapath1 performs ALU operation - Addition or Subtraction. (A0 + D0) or (A0 - D0)

5) Result is available in the Datpath1.PO

View solution in original post

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8 Replies
RodolfoGL
Employee

If your "calculation" can be performed in one clock cycle, then there is no need to store the input value. But if it takes multiple cycles, you might want to latch it to a register, in case the input changes during the "calculation".

If you don't latch it, you can save some macrocells from the UDBs.

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RaAl_264636
Contributor II

Hello@RodolfoGL 

I forgot to mention: the component uses parallel input/output to get the values, that's the reason for having two states. PI is used in both states. So it's not possible to do it in a single clock cycle. Sorry for the missing detail 😞

Are there any recommendations about the two implementations?

Regards

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RodolfoGL
Employee

Just to clarify, your calculations are done in hardware or firmware? I guess is in hardware.

If that's the case, there is no need to use the datapath PI/PO at all if you are not storing the data in the datapath FIFO or Dx registers. From my understanding, the PI and PO will be tied together in this case.

It would help if you share your Verilog code.

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RaAl_264636
Contributor II

Hello @RodolfoGL 

Just to clarify, your calculations are done in hardware or firmware? I guess is in hardware.

yes, the calculation is done in hardware by UDB datapath. The component is an 8-bit addition/subtraction component, where at least one of the operands comes from parallel input. The other operand also comes from parallel input or API access (Dx), optionally. The result is available on parallel out and can also be accessed by API (Fx). This is also the reason why two clock cycles are needed.

It would help if you share your Verilog code.

I'll share the complete component when it's finished, currently I'm verifying it. For the initial question it shouldn't be necessary to have the complete code posted now since it's a generic question and independend from the component function. That's why I hadn't posted code in my first posting. Or is the answer "depends on..."? In this case I can post the state machine snippet of the verilog file. A simplified implementation for my question would look like this:

always @(posedge Clk)
begin
  case(State)
    STATE_LOAD:
    begin
      StoreValue <= PI;  //store input values, variant #1
      RegResult <= PO;   //store ALU result from CALC state
      if(TrigRe)
      begin
//        StoreValue <= PI;  //store input values, variant #2
        State <= STATE_CALC;  //switch state to calculation
      end
    end
    STATE_CALC:
    begin
      //in this state PI is also used
      State <= STATE_LOAD;   //switch state to load
    end
  endcase
end

My question is about the 'StoreValue <= PI;' instruction, it can be always be done or only when the trigger is detected. As I wrote initially, currently I can't see a difference between the two. But since I don't have much experience, I wonder which one is better or if it doesn't matter. If it depends on what the component is intended for, I'd be happy if you can provide examples.

Regards

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RodolfoGL
Employee

When using PI in the datapath, you can't do ALU operations, so you will not be able to do subtraction or addition. Refer to the Component Author Guide section 11.6.4.1 Datapath / Limitations of the datapath.


Parallel input into the datapath is limited. This restricts the ability to use the datapath where other
hardware needs to provide a parallel value. Alternatives to parallel hardware loading may be
possible. If enough cycles are available, then a value can be serially shifted in. If the CPU or DMA
can get access to the value, then they can write the value to a FIFO or register in the datapath.

 You might need to use two dapatah and use a DMA to move the input data. Basically the flow would be:

1) Datapath0 captures the PI and load to the FIFO0

2) DMA triggers based on FIFO0 level. Transfer from Datapath0.FIFO0 to Datapath1.FIFO0

3) Datapath1 loads the FIFO0 to ALU

4) Datapath1 performs ALU operation - Addition or Subtraction. (A0 + D0) or (A0 - D0)

5) Result is available in the Datpath1.PO

View solution in original post

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RaAl_264636
Contributor II

Hello @RodolfoGL 

Okay, I'll check about those limitations, thank you for pointing me to it. If needed, I'll implement it the way you suggested.
Now, what about the position of storing the input values into verilog registers within the state machine? Only when trigger is detected?

Regards

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odissey1
Honored Contributor II

RaAl,

If bit width is low (8/16), then, I believe, making a pure PLD component in Verilog could be a simpler solution. I would estimate that for 8-bit parallel input and addition it will take less than 20% of the PLD space with operational frequency better than 48MHz.

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RodolfoGL
Employee

Yes, you could store the input bits to registers from the PLD. But you will not be able to leverage the datapath to do the substraction/addition. You would need to use a control register to drive the other operand and do the subtraction and addition with PLDs. You also need another 8-bit register to store the result.

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