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What is the oversampling ratio of PSoC5LP Delta Sigma Analog to Digital Converter?, I would like to have this info for the anti-aliasing filter design. I assume that it may over-sampled at the clock frequency (shown in the configuration window), but I can't find anything in the documentation about oversampling details.
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PSoC 5LP
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Hi,
The ADC decimation rate will vary according to resolution. The legal value of decimation can be from 2-256. This is adjusted according to the value in DEC_DR1 register. Kindly check the corresponding register in the Device Register TRM.
Best Regards,
Vasanth
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NiVa,
Due to it's specific operation DeltaSigma ADC usually doesn't need anti-aliasing filter. For the same reason it doesn't have oversampling mode.
The SAR ADC, on the other hand, needs anti-aliasing filter and often has oversampling mode (but not on PSoC5).
/odissey1
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Hi,
Any sampling process requires anti-aliasing filter, the delta-sigma has a relaxed requirements as it samples at much higher frequency (A quick search shows this blog for details https://e2e.ti.com/blogs_/archives/b/precisionhub/archive/2015/10/02/the-delta-sigma-advantage-to-an...)
The decimation filter (shown in page 2 of the datasheet) converts the over-sampled signal to the desired sampling rate, but I can't find the decimation factor (or oversampling ratio) from the datasheet.
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Hi,
The ADC decimation rate will vary according to resolution. The legal value of decimation can be from 2-256. This is adjusted according to the value in DEC_DR1 register. Kindly check the corresponding register in the Device Register TRM.
Best Regards,
Vasanth
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Thanks for the replay, I read the DEC_DR1 register value and it seems that the input is sampled (before decimation) at the clock frequency (at-least for my configuration).