Next Gen PsoC5, or PSoC7 ? Smart Sensor Controller

[UrPl_1236626]

Hi,

PSoC5 as a versatile MCU is in many ways better than stripped down PSoC6 which focus has gone to IoT/wearable battery powered devices. However there are still many "wired" devices in industry of modern smart sensors, so I wonder if we can collectively gather and vote for requirements for the next generation "PSoC5" sensor controller.

Some starting points from my mind and an amount of psoc projects created so far for the industry:

• m3 to be replaced with psoc6 core logic (m4 + m0 + crypto), and psoc5 has nice 105 oC rated while PSoC6 is still only 85 oC,
• technology shift for lower power, and bring in more RAM, in banks so that DMAs can independently (in parallel) work with different banks without stalling the CPUs; and CPUs between themselves; having m0+ as a comm controller in mind, and m4 as data post-processing controller
• DMA merge best of  psoc5 and psoc6
• increase of freq to 200 MHz, adopt GPIO speed from psoc6, but with synchronizers at I/O cells
• Two Delta Sigma, with improved 24-bit resolution @ 100 kSa/s, as many applications require parallel sampling of two values, missing saturation detector and post-sinc correction filter for low-latency; for WB and half-banding filters DFB is/can be used. ADS127L11 is an example of good (lower cost) A/D and the new L21.
• Bring SARs from PSoC4/PSoC6 which bring some post-processing
• Two DFB, existing DFB lacks some more memory to perform computation on larger sets as for FFT
• 100 Mbps LAN / TSN / SPE
• D/A improve resolution to 16-bit, with UDB direct connection for additional modulation/dithering
• UDB FIFO increase to at least 16-bytes, 4 bytes at higher speeds faces latency issues
• UDB 24/32-bit direct access, also on F0+F1 combined registers
• switching pump replace with a "fly-back" controller and  open-drain higher voltage fet so it can run in SEPIC mode with ultra low-start-up bias current, then direct connection to <60 V is easily implemented
• LVDS receiver - it is almost there with voltage reference, it's just missing a differential comparator between the two paired SIO pins
• CAN FD
• crystal -> VCXO (internal 16-bit D/A can be used for precise freq control), needed for low-jitter synchronous sampling, i.e. very good low-cost chip CDCE913

Applications:

• ratio-metric measurements, as strain-gauges, thermocouples with CJC, displacement sensors (AC frequency carrier)
• power measurements, and power analysis, voltage, current
• ...

[Len_CONSULTRON · Accepted solution]

UrPl_1236626

I'm in agreement with you that in general the PSoC5 is a 'better' micro.

Your 'wishlist' is a good start for future PSoC advance features.

I suggest to Infineon that they invite many PSoC-architecture enthusiasts to a special "PSoC Next-Gen" discussion conference.  Infineon can then understand from us what we find of value in the current offerings (feature 'keeps') and what we think may improve features and marketability of the next generation of PSoCs.

In the discussion, Infineon can illuminate to us what challenges they have had in previous architectures resulting in the current silicon direction shifts.  As a result, as a group, maybe we can suggest solutions to their challenges.

[AlenAn14]

Hi ,

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Warm Regards,
Alen