# Logic Level of "CY8C5467LTI-LP003" this chip?

Level 2
Level 2

"CY8C5467LTI-LP003" in the datasheet it mentioned that the power supply recommended is "1.7V to 5.5V" as per that is i power up the chip with the 5V, then the Logic level of "UART,I2C,SPI etc communication protocols" and the GPIO levels are between 5V and 0 as Ground right?

 CY8C5467LTI-LP003
1 Solution

# Re: Logic Level of "CY8C5467LTI-LP003" this chip?

Level 9
Level 9

JaVa,

Normally as moto stated, your voltage high drive levels are determined by the voltage supplied to the VDDIO pin if the pin output is set to STRONG.  If the pin is set to DIGITAL BIDIRECTIONAL as in the case of I2C interfaces, the output will ONLY drive low, float when high (hence needing a pullup to whatever voltage bias use chose).

The reason the output voltage will be lower than the VDDIO voltage due to the load current and the internal source resistance of the driver.  Assume for now the source resistance of a digital driver to be 100 ohms.  Therefore a 1mA current draw to the load when high will result in a voltage drop of 1mA*100ohms = 0.1V internally to the source resistance of the driver output.  With VDDIO = 4.7V the output should be 4.6V.

If you need more output control over the high voltage from the PSoC, there are two practical ways:

• Set the PSoC outputs to "BIDIRECTIONAL" or DIGITAL OUTPUT and "Open Drain, drives low" and use an external resistor.  The bias voltage of the pullup can be controlled to the desired maximum voltage.    This allow for some level-shifting/translation in your design.
Caution #1: Depending on the value of the pull-up resistor and load capacitance, you may be output frequency limited.  A lower value resistor (or lower value load capacitance) will allow faster output transitions.
Caution #2:  Try not to exceed VDDIO with the Bias voltage.  This can back-bias the VDDIO voltage and with enough current damage the PSoC.
• There are SIO pins on the PSoC.  With these pins you can set a regulated output voltage to these pins.  You can do so with an internal Vref or with a VDAC.

Question #1:  What is the design-intended voltage for your PSoC?  5V or 3.3V or other?

Question #2:  What are the voltage limitation to external circuit inputs or outputs?

Len

Len
"Engineering is an Art. The Art of Compromise."
5 Replies

# Re: Logic Level of "CY8C5467LTI-LP003" this chip?

Moderator
Moderator

Yes, it is. But I think if you can use an Oscilloscope to test. You could know it more clearly.

# Re: Logic Level of "CY8C5467LTI-LP003" this chip?

Level 9
Level 9
Distributor - Marubun (Japan)

Hi,

In the PSoC 5LP: CY8C54LP Family Datasheet

11.2 Device Level Specifications > Table 11-2. DC Specifications

11.4 Inputs and Outputs

So I would think that if you apply 5V to both VDDD and VDDIO

VOL 0.0V ~ 0.6V

VOH 4.4V ~ 5.0V

moto

# Re: Logic Level of "CY8C5467LTI-LP003" this chip?

Level 9
Level 9

JaVa,

Normally as moto stated, your voltage high drive levels are determined by the voltage supplied to the VDDIO pin if the pin output is set to STRONG.  If the pin is set to DIGITAL BIDIRECTIONAL as in the case of I2C interfaces, the output will ONLY drive low, float when high (hence needing a pullup to whatever voltage bias use chose).

The reason the output voltage will be lower than the VDDIO voltage due to the load current and the internal source resistance of the driver.  Assume for now the source resistance of a digital driver to be 100 ohms.  Therefore a 1mA current draw to the load when high will result in a voltage drop of 1mA*100ohms = 0.1V internally to the source resistance of the driver output.  With VDDIO = 4.7V the output should be 4.6V.

If you need more output control over the high voltage from the PSoC, there are two practical ways:

• Set the PSoC outputs to "BIDIRECTIONAL" or DIGITAL OUTPUT and "Open Drain, drives low" and use an external resistor.  The bias voltage of the pullup can be controlled to the desired maximum voltage.    This allow for some level-shifting/translation in your design.
Caution #1: Depending on the value of the pull-up resistor and load capacitance, you may be output frequency limited.  A lower value resistor (or lower value load capacitance) will allow faster output transitions.
Caution #2:  Try not to exceed VDDIO with the Bias voltage.  This can back-bias the VDDIO voltage and with enough current damage the PSoC.
• There are SIO pins on the PSoC.  With these pins you can set a regulated output voltage to these pins.  You can do so with an internal Vref or with a VDAC.

Question #1:  What is the design-intended voltage for your PSoC?  5V or 3.3V or other?

Question #2:  What are the voltage limitation to external circuit inputs or outputs?

Len

Len
"Engineering is an Art. The Art of Compromise."

# Re: Logic Level of "CY8C5467LTI-LP003" this chip?

Level 2
Level 2

hello LePo,

thanks for the information, mainly i want to drive he chip with the 5V as main input supply voltage, and as this PSoC gives option of VDDIO for multiple voltage levels, i want to utilize 1 VDDIO for the 3.3v logic level so that in future design in-case i have to work with some 3.3v hardware peripheral i can use my reserved VDDIO.

is that possible to run the whole chip with 5V supply and any 1 VDDIO with 3.3v , what will be connections for this please help me choose.

# Re: Logic Level of "CY8C5467LTI-LP003" this chip?

Level 9
Level 9

JaVa,

Most PSoC5LPs have four VDDIO pins.  you might be able to assign difference power sources for a set of GPIO pins.

Refer to this link for design criteria and limitations of using multiple power supply sources:  https://www.cypress.com/documentation/application-notes/an61290-psoc-3-and-psoc-5lp-hardware-design-...

Len

Len
"Engineering is an Art. The Art of Compromise."